Principal Embedded SW/FW Engineer (Bringup) - Bengaluru, multiple vacancies 

Job Summary

We have an exciting opportunity to be part of a collaborative, cross-functional development team validating cutting-edge, high-performance AI chips and platforms.

 You will play a key role in supporting new product introductions and post-silicon validation.

Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to provide technical guidance to other engineering team members. In this role, you can leverage our experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes.

The Team

The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team.

Responsibilities and Duties

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon
• Deploy silicon validation tests on first silicon and debugging them
• Develop automated test framework and regression test suites in Python to optimize validation efficiency
• Collaborate closely with engineers from many other disciplines on a variety of topics
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies
• Analyse test results, identify and debug failures/defects
• Contribute to shared test and validation infrastructure
• Provide feedback to architects

Candidate Profile 

Essential:

• Understanding of ML applications and their workloads
• A self-starter who can apply independent judgement
• A team player able to lead and support colleagues with difficult concepts
• Strong experience in Bare metal / embedded C/C++

• Excellent problem-solving, analytical & diagnostic skills

• Ability to work across teams and programming languages to find root causes of critical and complex issues

• Experience of the post-silicon validation process applied in digital ASIC environments

• Python, Linux

• Excellent communication skills and the ability to explain difficult concepts to resolve issues 

Desirable

• 10+ years  experience 
• Experience building and leading, multi-site teams
• Driver level experience with one or more of the following is highly desirable:

• PCIe
• Ethernet
• Memory technologies (LPDDR, DDR, HBM, …)
• Other peripherals such as I2C, I3C, SPI, …

• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable.
• Experience of Arm CPUs, System IP and debug tools.
• Experience of AMBA protocols.
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, 

Staff Embedded SW/FW Engineer (Bringup)

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.

Job Summary

We have an exciting opportunity to be part of a collaborative, cross-functional development team developing C code used to validate cutting-edge, high-performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation.

Working within the Post-Silicon Bringup team, you will be involved with bringing first silicon to life, developing code primarily in C to configure and exercise systems and sub-systems on new silicon devices, and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes.

The Team

The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. 

Responsibilities and Duties

• Plan, design, develop and debug silicon bringup sequences and test in bare metal C/C++ on FPGA/Emulator prior to first silicon
• Deploy configuration sequences and validation tests on first silicon and debug them
• Develop automated test framework and regression test suites in Python to optimize validation efficiency
• Collaborate closely with engineers from many other disciplines on a variety of topics
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies
• Analyse test results, identify and debug failures/defects
• Contribute to shared test and validation infrastructure
• Provide feedback to architects

Candidate Profile

Essential:

• Strong experience in Bare metal / embedded C/C++
• Good knowledge of digital ASICs.
• Be highly motivated, a self starter, and a team player 
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the post-silicon validation process applied in digital ASIC environments
• Python, Linux
• Excellent communication skills and the ability to collaborate with others to solve problems.
• Excellent problem-solving, analytical & diagnostic skills

Desirable:

• Driver level experience with one or more of the following is highly desirable:

• PCIe
• Ethernet
• Memory technologies (LPDDR, DDR, HBM, …)
• Other peripherals such as I2C, I3C, SPI, …

• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable.
• Experience of Arm CPUs, System IP and debug tools.
• Experience of AMBA protocols.
• Understanding of ML applications and their workloads.
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Position Overview 

We are seeking a Senior FPGA Verification Engineer with 4–8 years of experience to design, develop, and execute comprehensive verification strategies for complex FPGA designs. This role requires strong hands-on expertise in System Verilog and UVM, testbench architecture, and cross-functional collaboration with design and system teams. 

 Key Responsibilities: 

• Develop and maintain System Verilog/UVM-based verification environments for FPGA block-level and top-level designs  
• Create and execute verification plans, directed and constrained-random test scenarios, assertions, and functional coverage  
• Perform simulation-based verification of FPGA designs using industry-standard simulators  
• Drive debug and root-cause analysis of functional issues and work closely with FPGA RTL designers
• Integrate and maintain VIPs, scoreboards, checkers, and reference models  
• Support FPGA bring-up, validation, and debug activities on FPGA platforms and evaluation boards  
• Review FPGA RTL, verification code, and test plans to ensure quality and completeness  
• Mentor junior engineers and contribute to FPGA verification best practices
• Support regression runs, coverage closure, and release signoff 

Qualifications 

Education:  

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field 

Experience: 

4–8 years of hands-on experience in functional verification 

Preferred Qualifications:  

• Familiarity with cadence tools like Xcelium 
• Familiarity with Xilinx Vivado 
• Experience with hardware/software co-verification  
• Knowledge of high-speed interfaces (AXI, AXIStream, DDR, SPI)  

Soft Skills: 

• Strong analytical and debugging skills  
• Ability to work effectively in cross-functional teams  
• Excellent written and verbal communication skills  
• Self-driven with the ability to own verification tasks end-to-end  
• High attention to detail and commitment to quality 

Technology Stack: 

• Languages: System Verilog, Verilog, VHDL (working knowledge)  
• Verification Methodology: UVM  
• Simulation Tools: Xcelium, Questa, VCS  
• FPGA Tools: Xilinx Vivado  
• Debug Tools: SimVision  
• Scripting: Python, Tcl, Shell  
• Version Control: Git   

Physical Requirements 

• Ability to work in a standard office environment  
• Ability to use a computer for extended periods  
• Occasional lab work for FPGA bring-up and debug 

This job description may not be inclusive to the duties and responsibilities listed. Additional tasks may be assigned to the employee from time to time or the scope of the job may change as needed by business demands. 

WHO WE ARE

Optiver is a global market maker founded in Amsterdam, with offices in London, Chicago, Austin, New York, Sydney, Shanghai, Hong Kong, Singapore, Taipei and Mumbai. Established in 1986, today we are a leading liquidity provider, with close to 2,000 employees in offices around the world, united in our commitment to improve the market through competitive pricing, execution and risk management. By providing liquidity on multiple exchanges across the world in various financial instruments we participate in the safeguarding of healthy and efficient markets. We provide liquidity to financial markets using our own capital, at our own risk, trading a wide range of products: listed derivatives, cash equities, ETFs, bonds and foreign currencies.

In Asia Pacific, Optiver was one of the first global market makers to establish a presence in the region, with the incorporation our Sydney office in 1996. Since then, we have expanded our footprint by establishing offices in Taipei (2005), Hong Kong (2007), Shanghai (2012) and Singapore (2021). The business in Mumbai is newly established and deemed to be an integral part of the APAC strategy, with an anticipation of significant growth over the coming years.

WHAT YOU'LL DO

We are looking for an experienced Software Development Team Lead (C++ & FPGA) to lead our India Execution Team, focused on building Optiver’s next-generation ultra-low latency trading systems.

In this role, you will lead a hybrid team of C++ software engineers and FPGA developers, driving the design and delivery of systems that achieve best-in-market trade execution across Indian exchanges (NSE, BSE, MCX). You’ll work at the intersection of software and hardware, shaping how system architecture is split across software and the FPGA to optimise latency, throughput, and reliability.

You won’t be doing this in isolation - you’ll collaborate closely with established execution and FPGA teams in Sydney and Shanghai, while contributing to Optiver’s broader execution strategy across APAC.

As a leader, you’ll partner with trading, risk, compliance, and research teams locally in Mumbai to define and execute the vision for our execution platform. You’ll join an already established team with strong talent, focusing on scaling the team and maintaining a high-performance engineering culture, while remaining hands-on in system design across C++ and FPGA and contributing directly to C++ development.

Our engineers own problems end-to-end—from understanding trading challenges to designing, implementing, testing, and deploying solutions into live markets. Development is fast-paced and impactful, with features often reaching production within days.

Your responsibilities will include:

• Lead and grow a high-performance team of C++ and FPGA engineers, including hiring, mentoring, and performance management.

• Define and evolve the architecture of our ultra-low latency trading stack, balancing software and hardware design decisions.

• Design and implement high-performance C++ systems for order management, exchange connectivity, and risk controls.

• Guide the development of FPGA components and hybrid FPGA/software systems for latency-critical paths.

• Partner with trading and research teams to improve execution performance and ensure Optiver is #1 in execution for Indian markets.

• Contribute to the strategy and vision for Optiver’s Asia Pacific execution capability.

• Drive robustness and quality through strong engineering practices, including code reviews, testing, and production monitoring.

• Own and improve automated trading risk controls within our execution systems.

• Collaborate across global teams to share knowledge and influence broader system design.

WHO YOU ARE

We’re looking for a technically strong and people-focused leader with a background in building high-performance systems and a passion for developing teams. You should have:

• 5+ years of experience as a Software Engineer, with strong C++ experience building backend systems, client-server architectures, or distributed systems.

• 3+ years of demonstrated formal leadership experience.

• Experience developing or maintaining exchange connectivity systems or other high-reliability, latency-sensitive systems.

• Proven ability to solve technically challenging problems, with a pragmatic and results-driven mindset.

• Experience owning work across the full software development lifecycle - from requirements gathering through design, implementation, testing, and production delivery.

• Strong stakeholder management skills, with the ability to collaborate effectively with trading, research, and other business teams.

• Experience leading projects as a technical owner, driving delivery and influencing design decisions.

• Interest in working across software and hardware boundaries in hybrid C++/FPGA systems.

If you have any of these, we’re even more excited to hear from you:

• Experience working with FPGAs or embedded systems, or exposure to hardware/software co-design.

• Background in low latency systems within a similar trading firm.

• Experience directly leading a team.

WHAT YOU'LL GET

DIVERSITY AND INCLUSION

Optiver is committed to diversity and inclusion.

We encourage applications from candidates from any and all backgrounds, and we welcome requests for reasonable adjustments during the process to ensure that you can best demonstrate your abilities. Please let us know if you would like to request any reasonable adjustments by contacting the Recruitment team via careers@optiver.com.au.   

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Senior Emulation Engineer

Location: India - Remote

Job Description:

At EnCharge AI, we are building the next generation of AI compute silicon — purpose-built

for high-performance, low-power, and scalable AI inference. As an Emulation Engineer, you

will play a critical role in validating complex AI accelerator architectures on emulation

platforms before tape-out. This position is ideal for someone passionate about bridging the

gap between hardware and software in fast-paced, deep tech environments.

Responsibilities:

• Set up and maintain Siemens Veloce emulation and prototyping platforms

• Adapt SoC designs for Emulation and Prototyping

• Develop and debug emulation testbenches and system-level environments

• Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation.

• Collaborate with design and verification teams to isolate design issues and accelerate debug.

• Optimize performance of the emulation workloads and reduce turnaround time.

• Work with firmware/software teams to enable use of emulators for OS and driver testing.

Required Background:

• BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience.

• Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium)

• Experience with emulating high speed I/O interfaces such as PCIe and UCIe and memory technologies such as LPDDR and HBM

• Solid understanding of digital design, RTL (Verilog/SystemVerilog), and SoC architecture.

• Proficiency in hardware debug tools, waveform viewers, and logic analyzers

• Scripting skills (e.g., Python, Tcl, Perl) for automation and infrastructure development

• Familiarity with UVM, simulation, and testbench environments. SystemVerilog and UVM-based verification experience a plus

• Hand-on software development experience with C/C++ is a plus

Role Summary

Design, implement, and ship Bluetooth Controller firmware across BLE (Link Layer/MAC) and Bluetooth Classic (BR/EDR LM behaviors) on our SoCs. Work spans bring-up, timing & reliability, test/qualification, and cross-functional debug with RF, systems, and QA—hands-on from lab benches to release.

Key Responsibilities

• Firmware development (Controller): Implement and maintain controller features aligned to Bluetooth Core Spec 5.x and 6.x for BLE and Bluetooth Classic.
• Bring-up & stabilization: Bring up features on FPGA/eval boards/silicon; tune timing/latency paths in RTOS environments for BLE and Classic.
• Test & qualification support: support certification/interop; analyze sniffer/HCI logs and close issues with clear root cause.
• System-level debugging: Triage issues across firmware, drivers, and basic RF interactions; collaborate with Hardware/RF, Systems, and QA to land fixes.
• Tooling & automation: Contribute HCI test scripts, utilities, and CI checks that improve repeatability and coverage.
• Maintenance: Participate in code reviews, documentation, and sustaining engineering for released features.

Core Competencies

• Hands-on experience in Bluetooth controller firmware with understanding of BLE LL/MAC and Bluetooth Classic LM procedures.
• Strong embedded C skills (interrupts, memory-safe coding, RTOS concurrency).
• Comfort with UART/SPI/I²C and board bring-up workflows.
• Ability to work with sniffer/HCI logs (BLE and Classic) and embedded debuggers; strong analytical and troubleshooting ability.
• Organized, detail-oriented, proactive, and effective in cross-functional teams.
• Clear written and verbal communication.

Qualifications (Requirements)

• E./B.Tech/M.E./M.Tech in ECE/EE/CS (or equivalent practical experience).
• 5–9 years of embedded firmware experience on MCUs/SoCs with RTOS.
• Proficiency in C, version control, code reviews, and CI basics.
• Experience developing to Bluetooth Core Spec 5.x and 6.x at the controller level—covering BLE LL/MAC and exposure to Bluetooth Classic BR/EDR LM procedures.
• Exposure to system test, troubleshooting, and root-cause analysis of Bluetooth products.
• Basic RF awareness.
• Coexistence basics (Wi‑Fi/Bluetooth) and lab tools (oscilloscope, logic analyzer, power meter).
• Familiarity with open Bluetooth ecosystems (e.g., Zephyr/NimBLE).

You will do:

 Construct SoC level test benches using verification components developed at the IP level. Test bench architecture for 
random/directed testing, stimulus generation, and checking to include custom and off the shelf VIP/UVCs.
• Develop and execute SoC verification plans focused on IP block interoperability and SOC/System level. Develop and 
execute verification plans based on design specifications and collaboration with architects and designers.
• Develop RAL test plan at SOC/IP level and its implementation.
• Verify SoC using advanced verification methodologies.
• Construct HW/SW Co-Verification environment - test-benches, use-cases,
• APIs, sequences. Execute and Debug use-cases.
• Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modeling (TLM), HW 
emulation/acceleration, and SW driven verification.
• Work with design team to understand design intent and bring up verification plans and schedules.
• You will think through design corner cases and be able to write relevant cover points.
• Debug test cases and report verification result to achieve expected code/functional coverage goal. Utilize constrained 
random verification, functional coverage, code coverage and assertions to achieve goals.
• Assist in emulation, FPGA, prototyping efforts.
• Implement / maintain automated verification flows in languages such as Python, Perl/ Shell scripts.

Required Qualifications:

• BSEE or MSEE, with experience in ASIC development and/or FPGA prototyping
• 7+ years of experience in RTL design using Verilog, SystemVerilog
• Understanding of Digital Signal Processing theory, and mapping to design
• Experience in WiFi Physical Layer, and/or other Physical layer like Cellular (WiMax, LTE, NR), Bluetooth, Zigbee, UWB, and/or other Physical layer (Ethernet) technologies
• Ability to work independently, and proactively identify and resolve issues.
• Experience with Incisive/Excellium/VCS, Verdi, Jasper/Spyglass or equivalent tools
• Experience in partitioning, synthesis, placement, timing closure for FPGA and/or ASICs
• Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs.
• Enjoy debugging, and problem solving in a team environment.

Preferred Qualifications:

• • Master’s degree in engineering (or equivalent) or Bachelor’s degree in EE/EC/CS.
  • 10+ years of experience in design verification - Proven experience in full chip verification from test plan development to 
  tape-out sign-off. A good understanding of the complete verification life cycle (test plan, testbench through coverage 
  closure) 
  • Strong knowledge about multiple testbench architectures
  • Experience constructing chip-level System Verilog and UVM test bench environments, writing System Verilog Assertions 
  (SVAs), with embedded software design and test.
  • Track record of successfully executing block or chip-level verification plans.
  • HW/SW Co-Verification experience is a plus - Developing test benches, test cases/use-cases, APIs, their execution and 
  debug on a FPGA/Emulation platform.
  • Expertise in developing RAL using UVM methodology and able to write all the UVM component like monitor, 
  scoreboard, driver, agent etc from the scratch
  • Proficient working knowledge of AXI-lite/AXI-Stream/APB/AHB
  • Excellent debug skills, with experience debugging RTL in block and/or chip-level environments.
  • Proficient knowledge of VHDL, System Verilog, UVM, C and scripting languages like Python, Perl and Tcl.
  • Proficiency with Cadence design tools/environment and cadence UVC's is plus.
  • Excellent communication skills, energetic and self-motivated.
  • Work effectively with an off-site/off-shore design/DV team

Responsibilities & Desired skills:
• Construct SoC level test benches using verification components developed at the block/IP level. Test bench 
architecture for random/directed testing, stimulus generation, and checking to include custom and off the 
shelf VIP/UVCs.
• Develop and execute SoC verification plans focused on IP block interoperability and SOC/System level. 
Develop and execute verification plans based on design specifications and collaboration with architects and 
designers.
• Verify SoC using advanced verification methodologies
• Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and 
Debug use-cases.
• Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modeling 
(TLM), HW emulation/acceleration, and SW driven verification.
• Work with design team to understand design intent and bring up verification plans and schedules
• You will think through design corner cases and be able to write relevant cover points
• Debug test cases and report verification results to achieve expected code/functional coverage goal. Utilize 
constrained random verification, functional coverage, code coverage and assertions to achieve goals.
• Assist in emulation, FPGA, prototyping efforts.
• Implement / maintain automated verification flows in languages such as Python / Shell scripts.
• 5+ years of verification experience is required