The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

FPGAs and ASICs are critical pieces of our technology stack. We are looking for talented hardware developers to architect and design complex systems on a highly collaborative global team. In this role, you'll identify efficient ways to perform on-the-fly transformations of market data and implement models with complex data structures in RTL. Deep knowledge of SystemVerilog, FPGA internals and/or ASIC primitives, computer architecture, and vendor tool suites are essential to succeeding in this role. Expertise in networking protocols, CPU design, and/or machine learning accelerators is a big plus. No financial experience is necessary.

Responsibilities

• Collaborate with a cross-functional team to develop and deploy custom FPGA and/or ASIC solutions for a wide range of trading applications
• Investigate new technologies and tools
• Contribute to a nimble hardware development tech stack

Qualifications

• Ability to describe hardware designs at a high level, low level, or anywhere in between
• Brilliant design, optimization, debugging and problem solving skills
• Professional experience (2+ years) in RTL design for FPGA or ASIC
• Expert SystemVerilog development skills with a thorough understanding of the language 
• Expert on low level FPGA or ASIC architectures, with a deep understanding of what makes them "tick"
• Skilled in network communications, processing pipelines, and/or machine learning
• Working knowledge of Python and/or C++
• Comfortable in a Linux environment
• Strong verification experience
• Familiarity with AMD Vivado is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications 

• Superb debug and analytical skills 
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is seeking a Physical Design Engineer with a broad, versatile skillset to join our growing Hardware team. In this role, you will help deliver performance-critical ASICs and advance our physical design methodologies on leading-edge process nodes.

The Hardware team at HRT builds high-performance compute engines using FPGA and ASIC technology to drive low-latency trading decisions on global markets. We create custom solutions across the full spectrum of speed and sophistication, from bespoke circuits to world-class machine learning accelerators.

Responsibilities

• Drive design-for-test (DFT) methodologies and implementation 
• Contribute to physical implementation, from RTL handoff through GDSII on advanced process nodes 
• Partner on floorplanning and physical optimization for high-performance, latency-critical designs
• Close timing across multiple modes and corners while optimizing power, performance, and area (PPA)
• Diagnose and resolve physical design issues such as timing bottlenecks, congestion, and IR/EM violations
• Build, maintain, and improve repeatable, automated physical design flows
• Develop scripts and tooling to improve productivity, robustness, and insight into design behavior
• Collaborate closely with RTL, architecture, and other hardware engineers to influence design decisions early

Qualifications

• Experience working in high-performance ASIC design environments
• Strong fundamentals in digital logic, circuit design, and process technology
• Familiarity with DFT concepts and testing methodologies
• Strong scripting and automation skills (Python, Tcl, shell), including parsing and analyzing tool outputs
• Ability to design robust methodologies, diagnose complex failures, and improve physical design flows
• Applied use of statistics in analyzing timing, power, or design data (preferred)
• Hands-on experience with static timing analysis and timing closure methodologies
• Expertise using industry-standard physical design and signoff tools (e.g., Innovus, PrimeTime)

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

At Optiver we pride ourselves on being real engineers, not just coders. Our engineers work closely with traders to identify the business problems we face and determine how they should be solved. We apply a disciplined and scientific approach. We engineer simple, well-architected solutions that meet the dynamic needs of our traders. Our passion is to solve problems which really matter to the business, and we take pride in the quality of our solutions.

Hardware Engineers at Optiver build hardware-based trading systems ranging from low latency algorithms to high bandwidth computation. They are responsible for owning all aspects of the development process from ideation to implementation creating bespoke solutions to our complex trading problems. Their systems have little room for failure which add to the stability of the market, not detract from it. Working in close collaboration with software engineers and traders, hardware engineers deeply understand our trading problems and create dynamic, well-architected systems that make an impact in a matter of days and weeks rather than months and years.

What you’ll do: 

• Accelerate network infrastructure and trading system components with high-speed hardware designs.
• Research new low-latency techniques and platforms and identify opportunities for integration with our trading system.
• Work in a multidisciplinary team of traders, software developers, and infrastructure engineers.
• Leverage the best hardware available or build in-house versions to ensure our FPGAs can interface with cutting edge server hardware.
• Manage relationships with 3rd party vendors.

What you’ll get:

You’ll join a culture of collaboration and excellence, surrounded by curious thinkers and creative problem-solvers. Motivated by a passion for continuous improvement, you’ll thrive in a supportive, high-performing environment alongside talented colleagues, collectively tackling some of the toughest challenges in the financial markets.

In addition, you’ll receive:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• A Bachelor’s degree in CE, EE, CS, or related technical field.
• Experience designing, coding, testing, and verifying FPGAs and/or ASICs.
• Experience coding in VHDL, Verilog, SystemVerilog as well as C or C++.
• Experience with RTL synthesis, writing timing, area, and other relevant constraints.
• Experience with digital simulators and self-checking test benches.
• Experience supporting post-silicon bring-up and debugging a plus.
• Ability to work closely with software developers to rapidly deliver integrated systems.

Who we are:

At Optiver, our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency, and stabilising the market no matter the conditions. With a focus on continuous improvement, we prioritise safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Optiver Chicago’s culture parallels the energetic city we’re immersed in. Home to the Chicago Board of Trade, Chicago Board Options Exchange, and Chicago Mercantile Exchange, Chicago has established itself as the trading capital of the US. Active on leading US exchanges, Optiver’s Chicago office trades a wide range of products from listed derivatives to cash equities, ETFs, bonds and foreign exchange

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

Optiver is looking to add FPGA Engineers to its Automated Trading Systems (ATS) team. ATS solve a variety of problems with high degrees of difficulty: managing scarce bandwidth resources, responding to market events with extremely low latency, and automatically pricing diverse sets of financial instruments with near-zero error tolerance. We build systems with little room for failure which add to the stability of the market, not detract from it. These systems must be simple, flexible, and well-architected so they can quickly be changed to meet the dynamic needs of our traders. We already have a team of great engineers, but we need more.

Optiver Hardware Engineers:

• Accelerate network infrastructure and trading system components with high speed hardware designs.
• Research new low-latency techniques and identify opportunities for integration with our trading system.
• Work in a multidisciplinary team of traders, software developers, and infrastructure engineers.
• Leverage the best hardware available, ensuring our FPGAs can interface with cutting edge server hardware.

What you'll need:

• A Bachelor’s degree in CE, EE, CS, or related technical field
• Experience designing FPGAs in VHDL or Verilog. We use VHDL.
• Experience coding in VHDL, Verilog, SystemVerilog, C, or C++
• Experience with digital simulators and self-checking test benches a plus
• Ability to work closely with software developers to rapidly deliver integrated systems.

Who we are:

Optiver is a tech-driven trading firm and leading global market maker. As one of the oldest market making institutions, we are a trusted partner of 70+ exchanges across the globe. Our mission is to constantly improve the market by injecting liquidity, providing accurate pricing, increasing transparency and acting as a stabilising force no matter the market conditions. With a focus on continuous improvement, we participate in the safeguarding of healthy and efficient markets for everyone who participates.

Based in ‘The Domain’ neighborhood, Optiver’s Austin office serves as the firm’s innovation nucleus, with a strong focus on quantitative research, software and hardware engineering initiatives. With tech innovation an integral part of our core business, the booming city proved an ideal backdrop for our heavy investment into machine learning, research infrastructure and big data computing. What’s more, with world-class music, food and art scenes, as well as countless scenic outdoor activities, the quality of life for Austin Optiverians is second to none.

Are you excited by the idea of applying your hardware development expertise to power ultra-low-latency trading systems? Do you want to explore new architectures that push the limits of performance and help take some of our most sophisticated trading strategies to the next level? If so, we encourage you to read on! 

At CTC, we’re looking for a Senior FPGA Engineer to join our FPGA development team to do just that and more. As a member, you'll work closely with other specialists, traders, and quants to design and build the next generation of end-to-end trading systems. While helping craft our development environment and processes, you’ll architect solutions, influence design choices across teams, and see your work translate into real-time impact. 

Responsibilities

• Partner with a skilled team to define and implement a pragmatic architectural vision with a focus on ultra-low-latency and reliability. 
• Collaborate with senior technology leaders to continuously improve our trading platform design. 
• Build a deep understanding of trading workflows, quantitative models, and system performance needs while working with a multidisciplinary team. 
• Develop an implementation roadmap in partnership with Quant and Trading to deliver incremental improvements in trading performance and long-term architectural innovation. 
• Lead design implementation efforts, contribute to team code reviews, and champion best practices around performance, logic, standard methodologies and maintainability issues to ensure code-level consistency and scalability. 

Qualifications

• Proven experience and expertise with FPGA development. 
• Advanced proficiency using HDLs, with an emphasis on SystemVerilog or VHDL. 
• Comfortable working in Python and/or C++ for developing tools, testbenches, and integrations. 
• Demonstrated understanding of computer architectures. 
• Enthusiasm for applying modern, agile design and testing practices. 

Nice to Have 

• Experience in financial markets or trading environments. 
• Knowledge of common networking protocols like TCP/UDP and multicast.