Job Title: Hardware Design Engineer

Reports to: Director of Hardware Engineering

Department: Engineering

💼 About the role

We’re seeking an experienced hardware design engineer to expand our cryptographic hardware IP team. You would be joining a mature design team with a proven track record of delivering market leading cryptographic IP, your role would expose you to the latest cryptographic standards and allow you to develop for the latest technologies.

We hope that you have at least 5 years of experience working on hardware design of complex IPs targeted at deployment on latest generation FPGAs, preferably with some experience working with cryptographic and security IPs.

 We have been established since 2018, so you would be directly working with the founders and inventors of this deep tech startup. The technology is already a couple of years in the making, its feasibility having been established, funding secured, and it has a clear path to market. This is a great opportunity for career progression and to get a head start in a rapidly expanding segment of the technology industry.

⚒️ What you’ll be doing

• Design and implementation of hardware IP blocks and subsystems.
• Tailoring implementations to FPGAs
• Working with verification engineers to create verification and test plans.
• Creation of reliable, reusable and excellently structured hardware design flows.
• Providing feedback to architects on feasibility of implementation and specification quality.
• Ensuring clean lint and implementation reports for IP blocks and subsystems.

🎯 Required Skills And Qualifications

• A commitment to high quality engineering in all areas of their work, including advocating for the best long-term solutions over the easiest or quickest.
• Optimising designs for both area and performance in FPGA technologies.  
• Experience building hardware IP blocks from scratch, and owning the process from initial specification through to customer delivery.
• Confidence bringing up a design using a basic “designers testbench”.
• Experience with standard commercial EDA Design tooling flows.
• Knowledge of common bus protocols (e.g. AMBA AXI4, AHB).
• Experience building and simulating hardware/software co-designs.
• Confidence in debugging RTL simulations issues.
• Degree or equivalent in Electronics/Computer Science or other related discipline.

🖥️ Specific Technologies You Are Confident Using

• FPGA and emulation experience. We use Xilinx FPGAs extensively for prototyping and hardware/firmware co-development.
• Logical IP design using SystemVerilog.
• Version control using Git.
• Writing System and subsystem level tests in C, using CMake as a build system.
• Confidence using tools like Bash, TCL, CMake and Makefiles safely and sensibly.

👍 Preferred Skills And Qualifications

• Python scripting for flows and automation 
• Experience debugging gate level simulations.
• Knowledge of Industry standard SoC Security Architectures
• Knowledge of tamper resistance and/or power side-channel security countermeasures.
• Experience using Gitlab CI, or otherwise principles of continuous integration and testing.

🏆 Some of the perks of working with us:

• Unparalleled opportunities to learn and accelerated career development.
• A collaborative, team environment with people who truly love what they do.
• Competitive salary and share option scheme.
• Flexible and hybrid working, and a working from home budget.
• Private health insurance for yourself and your family.
• 25 days annual leave (plus bank holidays and two wellness weeks).
• 50% gym membership discount.
• The chance to work with a spirited, smart, and friendly team!

Interested? Apply today to be part of the future of secure hardware! 🚀

The Role 

The Senior Systems Software Engineer will be a member of the core team building the Quantum Key Distribution system. The focus is on high-performance Python services on Linux, algorithm optimization and acceleration (also via hardware offload), and the role spans defining software architecture, integrating with FPGA/embedded subsystems, and turning requirements into reliable, observable software.  

The Senior Systems Software Engineer leads and co-owns the overall internal QKD software architecture and client-facing software API. By setting engineering standards, mentoring, and unblocking delivery, they ensure predictable releases and a strong execution cadence. 

The Responsibilities 

The Senior Systems Software Engineer should expect to work in the following activities. 

• System architecture
  • Leading and co-owning the QKD software architecture: control plane services, key sifting/postprocessing integration, configuration management, monitoring, and external interfaces 
  • Defining module boundaries and service APIs; evolving the system toward clear data/control-plane separation 

• Efficient implementation and hardware/software integration
  • Designing and implementing high-performance Python services on Linux (asyncio, WebSockets, NumPy); profiling and tuning for latency and throughput
  • Developing, profiling, and optimizing QKD sifting and postprocessing algorithms (signal handling/processing, error correction/information reconciliation, LDPC, privacy amplification) to maximize key rate and minimize end-to-end latency; applying algorithmic improvements and implementation techniques (vectorization, concurrency/async, memory/layout tuning, C/C++ extensions, SIMD/CUDA/GPU/FPGA offload where appropriate)
  • Defining and maintaining robust interfaces with embedded/FPGA system components over UART/USB/PCIe/Ethernet; respecting realtime constraints and failure modes 
  • Guiding downstream system integration (WebSockets/gRPC/REST) and ensuring clear contracts and backward compatibility
  • Designing for test – building mocks/simulators and automated test systems 

• DevOps
  • Building and maintaining CI/CD with Docker and GitHub Actions; automated tests, static analysis, artifact management, and release pipelines
  • Establishing observability (structured logging, metrics, tracing) and operational runbooks; improving reliability and debuggability with SLOs/alerts
  • Embedding security and crypto hygiene by default: secure transport, secrets management, key handling, and coordination with cryptography stakeholders
  • Adding performance benchmarking and regression tracking for key rate and end-to-end latency; integrating profiling/flame graphs into CI and enforcing performance budgets 

The Requirements 

The Senior Systems Software Engineer is expected to have the following qualifications and experience. 

• 5+ years of Python development; 3+ years leading or co‑owning service/system architecture for a hardware‑first product 

• Strong Linux async Python (asyncio, WebSockets), concurrency (threads/processes), profiling/tuning 

• Proven custom hardware integration (MCU, FPGA) over UART/USB/PCIe/Ethernet 

• CI/CD with Docker and GitHub Actions; automated testing, static analysis, artifact management 

• Experience with GPU & CUDA acceleration/optimization; SIMD familiarity 

• Production observability (logging/metrics/tracing) and incident/debug practices 

• Working knowledge of relational/key-value/time-series stores (PostgreSQL/Redis/Prometheus)  

• Security by Default mindset: secrets, secure transport, key/crypto hygiene 

• Proficiency in written and spoken English 

• Ability to be on-site in Munich office several times per week 

• Applicants must have the right to work in Germany at the time of application. We do not provide visa sponsorship. 
• Must be eligible to obtain and maintain either (a) a U.S. Secret (or higher) security clearance or (b) an EU SECRET (or national equivalent) personnel security clearance. Employment is contingent on meeting applicable government security requirements; eligibility is determined by the competent authorities.

Good to have: 

• Experience with QKD systems, cryptography, or high‑rate data pipelines  

• Exposure to C/C++ for low‑level interfacing and FPGA/embedded ecosystems  

• Familiarity with gRPC/Protobuf, schema/versioning strategies, and Kubernetes 

The Role 

The Senior FPGA Developer will be a member of the core team building the Quantum Key Distribution system. The focus is end‑to‑end RTL ownership on AMD/Xilinx (Artix‑7, Kintex UltraScale): architect, implement, verify, and close timing on high‑rate interfaces and deterministic pipelines. The role also sets engineering discipline for FPGA development and mentors a junior engineer. 

The Senior FPGA Developer owns the FPGA architecture/codebase and collaborates closely with embedded/software to define clean contracts, ensure reliable bring‑up, and deliver reproducible, versioned bitstreams. 

The Responsibilities 

The Senior FPGA Developer should expect to work in the following activities. 

• RTL architecture, interfaces, and rather high-speed datapaths
  • Owning SystemVerilog RTL architecture/implementation for Artix‑7 and Kintex UltraScale (SystemVerilog, Vivado)
  • Implementing DDR3/DDR4 controllers integration, PCIe endpoint/DMA, and Ethernet/SFP paths; evaluating/integrating third‑party MAC/PCS IP
  • Building deterministic acquisition/timing/sifting layers — packetization, buffering, alignment; robust clocking/CDC/reset; custom low‑level protocols —  and bridging them to high‑throughput interfaces (DDR/PCIe)
  • Defining clear AXI/AXI‑Stream boundaries and register maps for SW/FW integration 

• Constraints, timing closure, and floorplanning
  • Authoring and maintaining XDC constraints (clocks, I/O, exceptions); achieving consistent timing closure across corners
  • Applying practical floorplanning (pblocks, placement guidance) and CDC methodology; analyzing reports and iterating for margin 

• Verification and CI
  • Establishing a professional verification environment with ModelSim/Questa; developing self‑checking testbenches and regression suites; integrating Python/cocotb co‑simulation with software harnesses/mocks; defining coverage goals (OSVVM/UVM as appropriate)
  • Building CI for lint/sim/synth/impl; archiving reports/bitstreams; automating regressions (including cocotb) and basic HW‑in‑the‑loop smoke tests 

• Bring-up, debug, and releases
  • Board bring-up and debug using ILA/logic analyzers; link training, memory calib, and protocol bring-up
  • Owning bitstream packaging, versioning, and release notes; ensuring reproducible builds and traceable artifacts 

• Cross-team collaboration and mentoring
  • Driving system integration with SW/FW: register/driver contracts, throughput/latency budgets, HIL
  • Mentoring a junior engineer; codifying style guides, reviews, and design documentation 

The Requirements 

The Senior FPGA Developer is expected to have the following qualifications and experience. 

• 5+ years production FPGA on AMD/Xilinx; expert SystemVerilog RTL 

• Demonstrated mentoring of junior engineers 

• Strong constraints/timing (XDC), CDC/reset, and practical floorplanning; consistent timing closure 

• Hands‑on DDR3/DDR4, PCIe endpoints/DMA, Ethernet/SFP; integrating/evaluating third‑party MAC/PCS IP 

• Strong verification background; experience with self-checking testbenches and regression testing, proficiency with ModelSim/Questa. Knowledge of OSVVM/UVM is a plus 

• CI for HDL: scripted sim/synth/impl (Tcl/Make/Python), lint, artifact/version management; board bring‑up and ILA‑based debug 

• System integration with SW/FW: register maps, driver contracts, HIL 

• Proficiency in written and spoken English 

• Ability to be on-site in Munich or Potsdam offices to work with hardware, when required
• Applicants must have the right to work in Germany at the time of application. We do not provide visa sponsorship.
• Must be eligible to obtain and maintain either (a) a U.S. Secret (or higher) security clearance or (b) an EU SECRET (or national equivalent) personnel security clearance. Employment is contingent on meeting applicable government security requirements; eligibility is determined by the competent authorities.

Good to have: 

• AXI4/AXI‑Stream expertise and DMA performance tuning 

• Formal verification exposure 

• Scripting for automation (Python/Tcl) and CI systems (GitHub Actions/Jenkins) 

• MicroBlaze/Zynq ecosystems and low‑level FW/C driver collaboration 

• Proven delivery on Artix‑7 and/or Kintex UltraScale with Vivado 
   

The Role 

The Electronics Design Engineer will be a member of the hardware team delivering low‑noise, high‑frequency mixed‑signal control and instrumentation for our QKD systems. The role spans end‑to‑end board design in Altium (schematics, layout, DFM/DFT), precision analog signal chains, prototype bring‑up/validation, and, where needed, STM32 (F4/H7) firmware in C for control, calibration, and integration. You will work with existing automated measurement software in Python and extend it where needed, collaborate closely with optics, FPGA, and software, and support manufacturing. 

The Responsibilities 

The Electronics Design Engineer should expect to work in the following activities. 

• Hardware design, prototyping, and validation 
  • Owning hardware architecture and component selection for precision, lownoise, and highfrequency performance 
  • Designing lownoise analog and mixedsignal schematics and PCB layout in Altium 
  • Managing prototype builds and vendors; executing bringup; precision and highfrequency measurements (DC accuracy, noise spectral density, longterm drift, frequency response); lab debug and reworks 
  • Working with existing automated measurement software (Python) and extending it where needed 
• Firmware development on STM32 and interfacing in Python (secondary scope)
  • Designing and modifying STM32 F4/H7 firmware in C (HAL)
  • Interfacing with Python drivers/scripts for control and data acquisition 

• Test automation and CI
  • Building and extending automated board/firmware test setups (Python; instrument control via VISA/SCPI through the existing automated measurement software) to capture logs/metrics
  • Establishing repeatable build/test pipelines for firmware and board validation; archiving artifacts, measurements, and calibration data 

• Manufacturing support and releases
  • Producing manufacturing packages; supporting vendors through fabrication and assembly; designing/maintaining simple test fixtures
  • Owning hardware/firmware versioning and release notes; maintaining traceable revisions 

• Cross‑team collaboration and documentation
  • Collaborating with optics/FPGA/software on interfaces, calibration, timing/latency budgets, and integration
  • Authoring design docs, analyses and budgets, calibration/bringup procedures, and change logs
  • Maintaining detailed experimental documentation in Confluence 

The Requirements 

The Electronics Design Engineer is expected to have the following qualifications and experience. 

• 5+ years analog/mixedsignal electronics design for R&D/instrumentation; strong Altium for schematics and PCB layout; DFM/DFT 

• Deep analog fundamentals: lownoise signal chains (e.g., highfrequency TIAs/preamps, ADC drivers, antialiasing/reconstruction filters), precision references/measurements, grounding/guarding/shielding, lowleakage layout 

• Ability to set/close noise and error budgets; tolerance/Monte Carlo and worstcase analysis; SPICEclass simulation (LTspice/PSPICE, etc.) 

• Lab expertise: precision/HF measurements (DC accuracy, noise spectral density, longterm drift, frequency response, temperature dependency); oscilloscopes, spectrum analyzers; VNA as applicable 

• Awareness of EMC/EMI and safety constraints; designforcompliance and precompliance testing 

• Python for lab/test automation and instrument control; Git‑centric workflow 

• Proficiency in written and spoken English 

• Ability to be on‑site in Munich or Potsdam offices to work with hardware, when required 

• Applicants must have the right to work in Germany at the time of application. We do not provide visa sponsorship. 
• Must be eligible to obtain and maintain either (a) a U.S. Secret (or higher) security clearance or (b) an EU SECRET (or national equivalent) personnel security clearance. Employment is contingent on meeting applicable government security requirements; eligibility is determined by the competent authorities.

Good to have: 

• STM32 F4/H7 exposure; C with HAL 

• Familiarity with STM32 bootloaders/updates (DFU/OTA) 

• Experience with calibration flows and production test fixtures

Why this role is exciting

At Vay, cars are remotely operated in real time from our Driving Centers in Berlin and Las Vegas,  a capability few companies worldwide have achieved on public roads. As a (Senior) Embedded Software Engineer, you will work on the safety-critical software stack that directly controls vehicle functions. The code you build will have a measurable impact on vehicle safety and reliability during real-world deployments.

What you’ll be driving

You will help build the safety-critical firmware that allows real vehicles to be operated remotely on public roads. Your work will directly influence how a car accelerates, steers, brakes, monitors itself for faults, and reacts in emergency situations. You’ll be:

• Designing, implementing, and verifying embedded software for safe remote operation of vehicles on public roads.
• Extending and maintaining validation infrastructure (simulation, HIL, in-vehicle)
• Improving automation in development workflows and tooling
• Collaborating with hardware, motion control, and systems engineers to solve challenges unique to remote driving
• If experienced in FPGA/VHDL, you’ll also be contributing to both microcontroller (C) and FPGA domains, broadening the impact of the role

What are we looking for

We’re looking for a (Senior) Embedded Software Engineer with a solid technical foundation and hands-on experience who is adaptable, eager to learn, and motivated by building safety-critical systems. You enjoy working close to hardware, care deeply about correctness and safety, and love seeing your code move real physical systems. You should apply if you have:

• Strong experience with C programming for embedded systems 
• Familiarity with RTOS (real-time operating systems)
• Experience with testing environments (simulation, HIL, in-vehicle validation)
• Problem-solving mindset, attention to detail, results-oriented

Nice to have’s

• FPGA programming in VHDL

Tech environment you will work in:

• Embedded C on microcontrollers
• RTOS-based real-time systems
• Simulation, hardware-in-the-loop (HIL), and real-vehicle validation
• CAN and CAN FD vehicle communication interfaces
• Safety-oriented coding standards such as ISO 26262 and MISRA-C
• Git-based version control and Linux-based CI/CD pipelines
• FPGA programming in VHDL: enables contribution across both microcontroller (C) and FPGA domains

Why choose Vay

💪  A global team of smart, motivated people from 30+ countries who love tackling hard problems and turning bold ideas into reality

🌍 Huge scope for impact in a fast paced environment

💰 ESOP virtual stock options: A stake in Vay’s future - not just a salary

🌴 Unlimited Paid Vacation Days

🎫 Subsidised Deutschland ticket (Berlin)

🏋️‍♂️ Subsidised Urban Sports Club or FitX Membership 

🚗 All Vay team members receive 30% off their Vay rides

🛍️ Exclusive external discounts

💼 €350 Home office budget 

✈️ Relocation financial assistance when relocating to Berlin 

📚 Fully funded German lessons 

🎊 Regular team events throughout the year

At Alpine Eagle, we’re building the future of counter-drone defence. We’re a fast-growing, international deep-tech company working at the intersection of aerospace engineering, defence systems, and machine learning. Our goal: create the world’s first swarm-based, airborne counter-drone system.

Modern conflicts show how quickly drones are reshaping the battlefield. Threats are rising, and today’s solutions aren’t keeping pace. We’re here to change that.

Alpine Eagle isn’t just a defence company. It’s a mission. Backed by an international team, strong funding, and a bold vision, we’re looking for people who want to shape the next generation of aerial security and build something that truly matters.

🎯 How you will make an impact:

As a Radar Software Engineer, you will be crucial in advancing our drone technology. You will develop, optimize and benchmark algorithms to further improve our radar perception with a multidisciplinary team to deliver next-generation drone solutions. 

• Design, Optimize and Benchmark Algorithms: Radar processing algorithms for drone-based applications such as raw signal processing and real-time object tracking. 

• Implement and Optimize for Target Platform: Implement selected algorithms for the target platform and optimize them for runtime and memory footprint. 

• Integration with Hardware: Partner with the hardware team to ensure seamless integration of computer vision models with drone systems. 

• Stay Updated: Keep abreast of the latest advancements in radar technology and signal processing with a special focus on aerial applications. 

• Code Reviews and Documentation: Participate in code reviews, maintain thorough documentation, and contribute to team discussions. 

✅ What you need to be successful:

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field. PhD is a plus. 

• Strong background in Radar Signal Processing (signal processing of radar raw data, radar object tracking) with 5+ years of experience. 

• Experience in embedded SW development (ARM / Neon, Cuda) 

• Strong proficiency in C++. 

• Proven experience with ROS2 or similar middleware. 

• A hands-on attitude and strong sense of ownership.  

• You approach complex problems systematically and document your results.  

What sets you apart from others: 

• Solid Python skills 

• Background in data analysis 

• FPGA development background 

• Experience with machine learning / AI in radar processing 

• Background in radar detection KPIs 

At Alpine Eagle, we are committed to diversity and equal opportunity. We welcome applications from all individuals regardless of ethnic origin, gender, religion, disability, age, or sexual identity.

Apply now!