Who we are

Axi was founded in Sydney in 2007 as a two-person startup. It has grown into a top global brokerage that’s trusted by tens of thousands of clients in 100+ countries. We offer a multi-asset trading service that allows clients of all levels to achieve their goals by trading and investing in global financial markets.

Our success is built on having top products, cutting-edge trading technology, award-winning service, and by having a great team of people working together all around the world – we hope you’ll enjoy getting to know them!

Axi is proud to have an honest and trusted reputation, with the Axi Group of companies operating under full financial regulation in different regions around the world, governed by ASIC, FCA, DFSA, FMA and CySec.

Let's talk about the cool stuff you do at Axi! 

The Performance & Reliability team works cross-functionally with domain PODs, SRE, and Architecture to shape and enforce performance standards, identify bottlenecks, and drive continuous optimization across services, APIs, and clients. You will be the voice for performance, helping teams design faster systems from inception.

Your EDGE Assignment/You Will

• Plan and conduct performance, load, stress, and soak tests for .NET Core microservices, React and React Native clients, SQL Server/Cosmos DB queries, and messaging systems.
• Profile services and applications to identify performance bottlenecks: CPU, memory, I/O, network, and database contention using tools like Perfview, dotTrace, Azure Monitor, and browser dev tools.
• Recommend and validate optimizations at code level (async patterns, caching, batching), database level (query tuning, indexing, partitioning), and infrastructure level (resource limits, autoscaling).
• Define and monitor performance budgets, SLOs/SLIs, and capacity plans for critical services, alerting teams to regressions or approaching limits.
• Work with Kubernetes/AKS teams on resource allocation, autoscaling strategies, and performance implications of deployments.
• Build and maintain performance dashboards and monitoring, visualizing metrics from Application Insights, Prometheus, or similar tools.
• Document performance best practices, anti-patterns, and decision trees to guide teams.

Technical Requirements

• Hands-on experience with performance testing frameworks and tools (e.g., JMeter, k6, Locust, custom harnesses).
• Strong understanding of .NET Core runtime behavior: async patterns, TPL, thread pool, GC, memory allocation, and profiling techniques.
• Proficiency with .NET profiling tools: Perfview, dotTrace, Application Insights, or equivalent; ability to interpret ETW traces and metrics.
• Solid knowledge of SQL Server performance: query plans, indexing strategies, execution time analysis, and workload characterization.
• Familiarity with NoSQL performance tuning: Cosmos DB throughput, partitioning, consistency trade-offs, and cost modeling.
• Understanding of browser and mobile performance: network waterfall analysis, rendering performance, JavaScript profiling, and memory leaks.
• Exposure to Kubernetes resource management: CPU/memory requests and limits, QoS classes, and impact on performance.
• Knowledge of observability tools: Application Insights, Prometheus, Grafana, or similar; ability to correlate metrics and traces to identify root causes.

Experience and Skills

• 4–8 years of experience in performance engineering, preferably for distributed, microservices-based systems.
• Strong debugging and troubleshooting mindset with ability to work backwards from customer impact to root cause.
• Experience collaborating with multiple teams across geographies to validate findings and drive implementation.
• Excellent written and verbal communication; ability to present findings and recommendations to both technical and non-technical audiences.

Axi's bag of delights 

• Competitive and attractive compensation.
• Extensive learning opportunities, such as professional training and certifications and soft skills development.
• 18 annual leave days per year.
• 12 sick days leave per year.
• Public holidays as declared by local government.
• Maternity leave as per law.
• Health Insurance. 

Axi's interview journey 

• Talent Acquisition Interview (45 minutes)
• Hiring Manager Exploratory Discussion (45–60 min)
• Technical Performance Round (60–75 min )
• Design & Debugging Round (60 min )
• Cultural Interview (30 minutes)

At Axi, we prioritise creating a workplace that upholds fairness and respect for all. We encourage every individual within our community to contribute towards a culture where everyone feels a sense of belonging and is treated with the dignity they deserve. We make all employment-related decisions—whether in hiring, compensation, training, performance reviews, or termination—based on merit and without bias, ensuring equal opportunities for everyone. We consciously work to identify and overcome any unconscious biases, with a commitment to fostering an inclusive environment where every employee and candidate feels genuinely welcomed and valued.

Please note that our organization works with recruitment agencies on a pre-approved basis only. A recruitment agency that wishes to submit candidate profiles or resumes for consideration must obtain prior written consent from our talent acquisition team. We do not accept unsolicited resumes from recruitment agencies, and we will not be responsible for any fees related to unsolicited resumes. Should we receive an unsolicited resume from a recruitment agency that does not have prior written consent, we will not be responsible for the payment any fees related to the recruitment of the candidate represented in the unsolicited resume.

You will do:

 Construct SoC level test benches using verification components developed at the IP level. Test bench architecture for 
random/directed testing, stimulus generation, and checking to include custom and off the shelf VIP/UVCs.
• Develop and execute SoC verification plans focused on IP block interoperability and SOC/System level. Develop and 
execute verification plans based on design specifications and collaboration with architects and designers.
• Develop RAL test plan at SOC/IP level and its implementation.
• Verify SoC using advanced verification methodologies.
• Construct HW/SW Co-Verification environment - test-benches, use-cases,
• APIs, sequences. Execute and Debug use-cases.
• Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modeling (TLM), HW 
emulation/acceleration, and SW driven verification.
• Work with design team to understand design intent and bring up verification plans and schedules.
• You will think through design corner cases and be able to write relevant cover points.
• Debug test cases and report verification result to achieve expected code/functional coverage goal. Utilize constrained 
random verification, functional coverage, code coverage and assertions to achieve goals.
• Assist in emulation, FPGA, prototyping efforts.
• Implement / maintain automated verification flows in languages such as Python, Perl/ Shell scripts.

Required Qualifications:

• BSEE or MSEE, with experience in ASIC development and/or FPGA prototyping
• 7+ years of experience in RTL design using Verilog, SystemVerilog
• Understanding of Digital Signal Processing theory, and mapping to design
• Experience in WiFi Physical Layer, and/or other Physical layer like Cellular (WiMax, LTE, NR), Bluetooth, Zigbee, UWB, and/or other Physical layer (Ethernet) technologies
• Ability to work independently, and proactively identify and resolve issues.
• Experience with Incisive/Excellium/VCS, Verdi, Jasper/Spyglass or equivalent tools
• Experience in partitioning, synthesis, placement, timing closure for FPGA and/or ASICs
• Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs.
• Enjoy debugging, and problem solving in a team environment.

Preferred Qualifications:

• • Master’s degree in engineering (or equivalent) or Bachelor’s degree in EE/EC/CS.
  • 10+ years of experience in design verification - Proven experience in full chip verification from test plan development to 
  tape-out sign-off. A good understanding of the complete verification life cycle (test plan, testbench through coverage 
  closure) 
  • Strong knowledge about multiple testbench architectures
  • Experience constructing chip-level System Verilog and UVM test bench environments, writing System Verilog Assertions 
  (SVAs), with embedded software design and test.
  • Track record of successfully executing block or chip-level verification plans.
  • HW/SW Co-Verification experience is a plus - Developing test benches, test cases/use-cases, APIs, their execution and 
  debug on a FPGA/Emulation platform.
  • Expertise in developing RAL using UVM methodology and able to write all the UVM component like monitor, 
  scoreboard, driver, agent etc from the scratch
  • Proficient working knowledge of AXI-lite/AXI-Stream/APB/AHB
  • Excellent debug skills, with experience debugging RTL in block and/or chip-level environments.
  • Proficient knowledge of VHDL, System Verilog, UVM, C and scripting languages like Python, Perl and Tcl.
  • Proficiency with Cadence design tools/environment and cadence UVC's is plus.
  • Excellent communication skills, energetic and self-motivated.
  • Work effectively with an off-site/off-shore design/DV team