𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟭𝟬𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟮𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟭𝟬-𝟮𝟬 𝗟𝗣𝗔)

Experience: 4+ yrs

Location: Bengaluru

Job Type: Full-time

We are seeking a highly skilled Senior IO Design Engineer to contribute to the design and implementation of advanced SoC IO architectures. This role is ideal for engineers with strong expertise in pad ring planning, IO implementation, bump map definition, and physical design handoff. You will work closely with cross-functional engineering teams to develop robust, high-performance IO solutions that meet product, packaging, and silicon requirements.

As a Senior IO Design Engineer, you will play a critical role in defining IO connectivity, optimizing pad ring layouts, supporting package integration, and ensuring seamless collaboration across architecture, physical design, verification, and validation teams. This position offers the opportunity to work on cutting-edge semiconductor technologies and complex SoC development programs.

Requirements

Key Responsibilities

• Plan, design, and optimize pad rings, bump maps, and package substrate layouts for advanced SoC designs.
• Develop and maintain IO connectivity, pad ring definitions, and bump pattern implementations.
• Generate and validate physical design handoff deliverables, including pad ring DEF files, Verilog netlists, and related implementation data.
• Collaborate with architecture, physical design, package engineering, technology, and foundry teams throughout the development lifecycle.
• Support verification, emulation, ASIC validation, and silicon debug activities by analyzing IO-related issues and implementing design improvements.
• Optimize IO placement, connectivity, and implementation to meet performance, manufacturability, and packaging requirements.
• Ensure compliance with IO design standards, package constraints, and implementation best practices.
• Participate in design reviews, technical discussions, and cross-functional planning sessions.
• Develop automation scripts and improve IO design workflows wherever applicable.
• Contribute to continuous improvement initiatives focused on design quality, productivity, and engineering excellence.

What Makes You a Great Fit

• 4+ years of hands-on experience in IO Design, pad ring planning, bump map definition, and advanced SoC implementation.
• Strong understanding of IO library cells, IO standards, and high-speed interfaces such as SerDes, DDR, PCIe, and CXL.
• Experience using IO planning and implementation tools such as Orbit IO, ISP, or equivalent EDA platforms.
• Hands-on experience generating IO implementation deliverables, including pad ring DEF files, IO netlists, and bump assignments.
• Strong proficiency in Verilog/SystemVerilog with a solid understanding of digital hardware design principles.
• Familiarity with scripting languages for automation is an added advantage.
• Strong analytical, debugging, and problem-solving skills with attention to detail.
• Excellent written and verbal communication skills with the ability to collaborate effectively across multidisciplinary engineering teams.
• Ability to work independently while managing multiple technical priorities in a fast-paced semiconductor development environment.
• Passion for delivering high-quality, scalable, and innovative semiconductor solutions.