Join Tenstorrent and help build the next generation of AI and CPU hardware. You'll drive microarchitecture and RTL development for cutting-edge digital IPs powering industry-leading AI/ML accelerators and CPUs, working across design, debug, test, and silicon bring-up. This is a unique opportunity to shape groundbreaking hardware from concept to production while collaborating with some of the industry's top engineers.

This role is remote, based out of North America or Taiwan.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced RTL and microarchitecture engineer with a strong background in complex ASIC, SoC, or chiplet development.
• Hands-on experience with Verilog-based design, industry-standard simulation and synthesis tools, and complex digital subsystem integration.
• Skilled at solving challenging logic, debug, and system-level design problems across pre-silicon and post-silicon environments.
• Effective collaborator who works closely with architecture, verification, physical design, DFx, and silicon validation teams.
• Bonus experience with open-source hardware projects, DFT/DFD methodologies, scan test, MBIST, JTAG, SoC debug architectures, or RISC-V CPU cores.
• You have a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science, and 5+ years of relevant industry experience.

What We Need

• Experience designing and implementing RTL for complex digital subsystems, fabrics, debug and test subsystems, or SoC-level integrations.
• Strong understanding of microarchitecture development and industry-standard protocols such as AXI, AHB, APB, I3C, and SPI.
• Ability to evaluate and optimize power, performance, and area (PPA) tradeoffs while delivering high-quality RTL.
• Proven debugging skills across both pre-silicon and post-silicon environments, including silicon bring-up and root-cause analysis.
• Familiarity with DFT/DFD concepts, including scan test, MBIST, JTAG, ATPG, or chip-level debug architectures, is highly valued.

What You Will Learn

• How next-generation CPU and AI accelerator chiplets are architected, integrated, tested, and brought to production silicon.
• Deep exposure to system management, security, debug, test, and large-scale SoC integration challenges.
• Opportunities to collaborate with experts across architecture, design verification, DFx, physical design, and silicon validation teams.
• Hands-on experience with advanced chiplet architectures, debug infrastructures, and the full silicon development lifecycle.
• Exposure to leading-edge AI hardware development and emerging open-source technologies, including RISC-V ecosystems.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.