This role is for one of the Weekday's clients

Salary range: Rs 1000000 - Rs 1500000 (ie INR 10 - 15 LPA)

Min Experience: 2+ years

Location: Bengaluru
JobType: full-time

We are looking for a talented Physical Design Engineer – EMIR with 2–6 years of experience in power integrity and reliability analysis for advanced semiconductor designs. The ideal candidate should have strong expertise in EMIR (Electromigration and IR Drop Analysis), with hands-on experience in Route EMIR, Static IR Analysis, Dynamic IR Analysis, Signal EM, and Power EM. You will play a critical role in ensuring robust power delivery networks and reliable chip implementation across advanced technology nodes while working closely with Physical Design, STA, and Design teams.

This role offers an excellent opportunity to contribute to cutting-edge SoC development and solve complex power integrity challenges in high-performance designs.

Requirements

Key Responsibilities

• Perform comprehensive EMIR analysis across multiple stages of the Physical Design flow.
• Execute Route EMIR analysis to validate routing quality and identify electromigration and IR drop issues.
• Conduct Static IR Drop analysis to verify voltage integrity under worst-case operating conditions.
• Perform Dynamic IR Drop analysis by considering switching activity and real-time power consumption.
• Analyze and resolve Signal EM violations to ensure long-term signal reliability.
• Perform Power EM analysis to validate current density across power grids and eliminate reliability risks.
• Debug EMIR violations and collaborate with implementation teams to develop effective optimization strategies.
• Work closely with Physical Design engineers to optimize power grid architecture and improve overall chip reliability.
• Interpret analysis reports, identify root causes, and implement corrective actions to achieve signoff quality.
• Support tape-out activities by ensuring all power integrity and electromigration checks meet signoff requirements.
• Collaborate with cross-functional teams including Floorplanning, Placement, CTS, Routing, STA, and Design teams to resolve implementation challenges.
• Contribute to methodology improvements and automation initiatives to enhance EMIR analysis efficiency.
• Maintain documentation of analysis results, methodologies, and best practices.

Required Skills

• 2–6 years of experience in Physical Design with a strong focus on EMIR analysis.
• Hands-on expertise in:
• Route EMIR
• Static IR Analysis
• Dynamic IR Analysis
• Signal EM
• Power EM
• Strong understanding of semiconductor Physical Design flow including Floorplanning, Placement, CTS, Routing, and Signoff.
• Experience in identifying and resolving electromigration and IR drop issues.
• Knowledge of power grid design, power delivery networks (PDN), and reliability analysis.
• Strong analytical and debugging skills with the ability to identify root causes of power integrity violations.
• Familiarity with advanced technology nodes and low-power design methodologies.
• Excellent problem-solving, communication, and collaboration skills.

Good to Have Skills

• Experience in scripting using TCL, Python, Perl, or Shell for automation and workflow optimization.
• Knowledge of EDA tools used for EMIR and Physical Design signoff.
• Exposure to methodology development and process automation.
• Understanding of timing closure and Physical Verification concepts.

Preferred Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
• Experience working on complex SoC designs at advanced process nodes.
• Ability to work in fast-paced, collaborative engineering environments.

Why Join Us?

• Work on next-generation semiconductor products and advanced silicon technologies.
• Collaborate with highly experienced Physical Design and Signoff engineers.
• Gain exposure to challenging EMIR and power integrity problems across large-scale SoC designs.
• Opportunity to contribute to automation, methodology development, and advanced implementation flows.
• Continuous learning, technical growth, and career advancement in semiconductor design and signoff engineering.