𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟱𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟰𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟱-𝟰𝟬 𝗟𝗣𝗔)

Experience: 2+ yrs

Location: Bengaluru, Karnataka, India, Hyderabad, Telangana, India

Job Type: Full-time

We are looking for a highly motivated Physical Design Engineer to join our semiconductor engineering team and contribute to the implementation and optimization of complex ASIC and SoC designs across advanced technology nodes. This role is ideal for professionals with strong expertise in Physical Design, Place and Route (PNR), Static Timing Analysis (STA), and EMIR (Electromigration & IR Drop Analysis) who are passionate about delivering high-performance, power-efficient, and manufacturable silicon solutions.

As a Physical Design Engineer, you will work closely with RTL, DFT, STA, Signoff, and Verification teams to drive the physical implementation flow from floorplanning through timing closure and final signoff. You will play a key role in optimizing performance, power, and area (PPA), resolving implementation challenges, and ensuring that designs meet timing, signal integrity, power integrity, and reliability requirements. This position offers the opportunity to work on cutting-edge semiconductor technologies while collaborating with cross-functional engineering teams in a fast-paced and innovation-driven environment.

Requirements

Key Responsibilities

• Execute end-to-end physical design activities including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization, and physical verification.
• Perform Place and Route (PNR) implementation while optimizing performance, power, and area (PPA) targets.
• Conduct Static Timing Analysis (STA) and support timing closure across multiple process, voltage, and temperature (PVT) corners.
• Perform EMIR (Electromigration and IR Drop) analysis and implement corrective actions to ensure power integrity and design reliability.
• Analyze and resolve setup, hold, congestion, signal integrity, and physical design violations.
• Collaborate with RTL, DFT, STA, Signoff, and Verification teams to resolve implementation challenges and improve overall design quality.
• Support engineering change orders (ECOs) and incremental implementation throughout the design lifecycle.
• Execute physical verification checks including DRC, LVS, antenna, and density analysis while ensuring compliance with foundry guidelines.
• Develop and enhance automation scripts using TCL, Python, or Perl to improve physical design productivity and workflow efficiency.
• Participate in design reviews, implementation planning, and signoff activities while contributing to continuous process improvement and engineering best practices.

What Makes You a Great Fit

• 2+ years of hands-on experience in ASIC/SoC Physical Design and implementation.
• Strong expertise in Place and Route (PNR) using industry-standard EDA tools such as Cadence Innovus or Synopsys ICC2.
• Solid understanding of Static Timing Analysis (STA), timing closure methodologies, and signoff processes.
• Hands-on experience performing EMIR (Electromigration and IR Drop) analysis and implementing power integrity optimizations.
• Good understanding of floorplanning, CTS, routing, physical verification, ECO implementation, and PPA optimization.
• Familiarity with advanced semiconductor technology nodes and modern physical design methodologies.
• Proficiency in scripting languages such as TCL, Python, or Perl for automation and workflow enhancement.
• Strong analytical, debugging, and problem-solving skills with attention to detail.
• Excellent communication and collaboration skills with the ability to work effectively in cross-functional engineering teams.
• A passion for semiconductor design, continuous learning, and delivering high-quality, reliable silicon solutions in a fast-paced engineering environment.