𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟰𝟬𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟲𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟰𝟬-𝟲𝟬 𝗟𝗣𝗔)

Experience: 10+ yrs

Location: Bengaluru

Job Type: Full-time

We are looking for an experienced Physical Design Engineer to drive end-to-end physical implementation of complex semiconductor designs. The role involves taking designs from netlist through floorplanning, placement, clock-tree synthesis, routing, timing closure, physical verification, and sign-off.

The ideal candidate will have deep hands-on expertise with Cadence Innovus, strong knowledge of STA, PNR, floorplanning, timing optimization, and physical design methodologies, and the ability to independently handle challenging implementation and closure activities on advanced designs.

Requirements

Key Responsibilities

• Own the end-to-end physical design flow from netlist to final sign-off.
• Perform chip/block-level floorplanning, power planning, placement, CTS, routing, and physical optimization.
• Use Cadence Innovus for physical implementation, optimization, and PNR activities.
• Analyze and resolve timing violations using Static Timing Analysis (STA) techniques.
• Work closely with STA teams to achieve timing closure across setup, hold, and other critical timing scenarios.
• Optimize designs for performance, power, area, congestion, and signal integrity.
• Develop and execute effective floorplanning and partitioning strategies based on design requirements.
• Identify and resolve congestion, routing, placement, clock, and physical design challenges.
• Support implementation across multiple design stages and ensure smooth progression toward sign-off.
• Collaborate with RTL, synthesis, DFT, STA, verification, and physical verification teams to resolve cross-functional issues.
• Analyze implementation reports and identify opportunities for improving PPA and overall design quality.
• Debug complex physical design issues and drive root-cause analysis and corrective actions.
• Contribute to improving physical design flows, methodologies, automation, and overall team productivity.
• Support design reviews and provide technical guidance to junior physical design engineers.

What's Makes You a Great Fit

• 10+ years of hands-on experience in semiconductor physical design and implementation.
• Strong expertise in the complete PNR/physical design flow.
• Extensive experience with Cadence Innovus and related physical implementation tools.
• Strong understanding of floorplanning, placement, CTS, routing, optimization, and timing closure.
• Deep knowledge of STA, including setup/hold analysis and timing optimization.
• Strong understanding of physical design constraints and their impact on power, performance, and area (PPA).
• Experience debugging congestion, timing, placement, routing, and clock-related issues.
• Strong understanding of semiconductor design flows and interaction between RTL, synthesis, STA, DFT, and physical implementation.
• Ability to independently own complex blocks or projects and drive them through implementation and closure.
• Strong analytical and problem-solving skills with excellent attention to detail.
• Effective communication and collaboration skills with cross-functional engineering teams.
• Ability to mentor engineers, contribute to methodology improvements, and take technical ownership of challenging physical design problems.