This role is for one of Weekday’s clients

Min Experience: 4+ years
Location: Hyderabad, Bengaluru
JobType: full-time

We are seeking a skilled Design Verification Engineer with 4–10 years of experience in semiconductor verification and digital design validation. The ideal candidate will have strong hands-on expertise in Gate Level Simulation (GLS) and PCIe verification, along with a solid understanding of functional verification methodologies. You will be responsible for developing and executing verification strategies, debugging simulation issues, and ensuring that designs meet functional, timing, and quality requirements before tape-out.

This role requires close collaboration with RTL designers, verification engineers, physical design teams, and other cross-functional stakeholders to identify issues early and deliver robust, production-ready silicon designs.

Requirements

Key Responsibilities

• Develop, maintain, and execute comprehensive verification plans for complex digital designs and SoC components.
• Perform Gate Level Simulation (GLS) to validate synthesized and implementation-level netlists against functional and timing requirements.
• Analyze GLS results, identify simulation mismatches, and debug issues related to timing, reset behavior, X-propagation, clock-domain interactions, and synthesis effects.
• Work extensively on PCIe verification, validating protocol functionality, link initialization, data transfers, error handling, and compliance-related scenarios.
• Develop and maintain simulation environments, testbenches, test cases, and regression suites.
• Analyze RTL-to-gate-level differences and investigate functional or timing-related issues across different stages of the design flow.
• Collaborate with RTL, design, physical design, DFT, and system teams to resolve verification and integration issues.
• Execute functional, corner-case, stress, and regression testing to achieve high verification coverage.
• Debug simulation failures using waveform analysis and industry-standard EDA tools.
• Contribute to improving verification methodologies, automation, coverage, and regression efficiency.
• Document verification results, bugs, root-cause analysis, and closure activities.

Must-Have Skills

• 4–10 years of experience in ASIC/SoC Design Verification.
• Strong hands-on experience with GLS (Gate Level Simulation).
• In-depth understanding of Gate Level Simulation flows, including netlist simulation, timing annotation, SDF concepts, and post-synthesis/post-layout verification.
• Strong experience with PCIe, including protocol concepts, link training, transaction handling, error scenarios, and debugging.
• Good understanding of digital design concepts, RTL simulation, clocks, resets, timing, and X-propagation.
• Strong debugging and problem-solving skills with the ability to analyze complex simulation failures.
• Experience working with industry-standard simulation and verification tools.

Good-to-Have Skills

• Strong programming and verification experience using SystemVerilog (SV).
• Hands-on experience with UVM (Universal Verification Methodology).
• Experience developing reusable UVM components, sequences, drivers, monitors, scoreboards, and functional coverage.
• Knowledge of PCIe verification IPs and protocol-level verification methodologies.
• Familiarity with scripting languages such as Python, Perl, or Tcl for verification automation.
• Experience with regression management, coverage analysis, and verification infrastructure.
• Exposure to post-layout verification and advanced SoC integration flows.