Job Description:
At Astera Labs, we are looking for motivated Senior / Tech Lead Post-Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness. The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar.

Basic Qualifications:

• Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥3 years’ experience testing, supporting or developing complex SoC/silicon products and high-speed IO/SerDes electrical interface for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, preferably as a tech lead.

Required Experience:

• Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3x Ethernet.
• Strong problem-solving skills, ability to solve problems independently.
• Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, and both NRZ and PAM4 signaling.
• Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration.
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

• Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels
• Familiarity with PCIe or Ethernet especially Electrical Compliance sections
• Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces
•  Working knowledge of C or C++ for embedded FW
•  Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling
•  Working knowledge of common serial data specifications such as I2C, SPI, etc
•  Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $148,500 USD - $165,000 USD for Senior level, and $175,000 USD - $195,000 USD for Staff level.