Über diese FPGA Silicon Design Engineer Stelle bei Altera
Job Details:
Job Description:
*This position does not provide Altera immigration sponsorship* Must be authorized to work in the United States without employer-sponsored immigration support for this position and meet all applicable eligibility requirements associated with supporting a U.S. government contract.
About Altera
At Altera™, our independence as the world’s largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of FPGA expertise, our mission is to deliver programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets such as AI, cloud, networking, and edge.
About the Role
Join Altera as an FPGA Silicon Design Engineer and contribute to the design, verification, implementation, and silicon bring-up of next-generation FPGA devices. In this role, you will develop complex digital logic and RTL while supporting the full ASIC implementation flow, from synthesis through physical design, timing closure, power analysis, and production-ready silicon.
You will work closely with architecture, design verification, physical design, software, firmware, and product engineering teams to deliver high-performance, power-efficient, and feature-rich FPGA solutions. The ideal candidate combines strong digital design expertise with hands-on experience in backend ASIC physical design flows and a disciplined approach to technical execution.
Responsibilities
Architect, design, and implement complex digital logic for FPGA silicon, including general-purpose logic, specialized blocks, control logic, and interconnects.
Develop, review, and maintain production-quality RTL using Verilog and/or SystemVerilog in accordance with design specifications and established coding practices.
Define and execute comprehensive design verification plans using industry-standard methodologies, including UVM, constrained-random verification, and SystemVerilog Assertions.
Execute and support the backend ASIC physical design flow, including synthesis, floorplanning, placement, clock-tree synthesis, routing, static timing analysis, timing closure, and power analysis.
Analyze design quality across performance, power, and area (PPA) objectives and implement optimizations to achieve product-level targets.
Use industry-standard EDA tools to simulate, synthesize, implement, analyze, and debug design blocks and full-chip integrations.
Collaborate with architecture, verification, physical design, software, firmware, and product engineering teams to define specifications, resolve design issues, and manage integration dependencies.
Contribute to silicon bring-up, post-silicon debug, characterization, and root-cause analysis of hardware, RTL, timing, and system-level issues.
Develop and maintain design specifications, architecture documentation, implementation collateral, verification plans, analysis reports, and technical presentations.
Participate in design and code reviews, provide actionable technical feedback, and communicate risks, status, and trade-offs to cross-functional stakeholders.
Use scripting and automation to improve design, verification, implementation, analysis, and regression workflows.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$149,100 - $213,015 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
#LI-MD1
Qualifications:
Minimum Qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, plus 8+ years of industry experience in FPGA or ASIC silicon design.
Must be authorized to work in the United States without employer-sponsored immigration support for this position and meet all applicable eligibility requirements associated with supporting a U.S. government contract.
5+ years of experience designing and implementing complex digital logic and RTL using Verilog and/or SystemVerilog.
5+ years of hands-on experience with backend ASIC physical design flows, including synthesis, floorplanning, placement, clock-tree synthesis, routing, static timing analysis, timing closure, and power analysis.
5+ years of experience using industry-standard EDA tools for simulation, synthesis, place-and-route, static timing analysis, power analysis, and physical design implementation, such as tools from Synopsys, Cadence, Siemens, or equivalent.
5+ years of experience applying digital design principles involving clock-domain crossing, reset architecture, clocking, asynchronous interfaces, finite-state machines, pipelining, and low-power design techniques.
5+ years of experience developing and executing verification strategies using SystemVerilog, UVM, SystemVerilog Assertions, simulation, waveform analysis, and coverage-based debug.
5+ years of experience developing automation, modeling, or analysis scripts using Python, Perl, Tcl, Shell, or equivalent scripting languages in a Unix/Linux environment.
5+ years of experience analyzing and resolving complex design issues through root-cause debug, technical trade-off evaluation, and cross-functional collaboration.
5+ years of experience communicating technical information through design reviews, specifications, implementation reports, verification reports, and other engineering documentation.
Preferred Qualifications
Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, plus 5+ years of ASIC or FPGA design experience.
Experience with FPGA architecture, programmable logic resources, configuration controllers, or network-on-chip architectures.
Experience supporting silicon bring-up, post-silicon validation, hardware characterization, or production readiness activities.
Experience with power-intent methodologies, low-power design, formal verification, linting, CDC analysis, or equivalence checking.
Experience with revision-control systems such as Git or Perforce.
Demonstrated ability to mentor engineers, influence technical decisions, and deliver results in a collaborative, cross-functional environment.
