💼What You'll Do

• Execute the design and development of Radiation Hardened LEAP Standard Cell Libraries across multiple advanced foundry technology nodes.
• Generate and validate new standard cells and IP, including combinatorial logic, sequential logic, and power management cells.
• Leverage in-house software and industry-standard SPICE tools to calculate radiation-induced error rates to ensure circuit resilience.
• Execute advanced library characterizations to optimize Power, Performance, and Area (PPA) in harsh environments.
• Collaborate directly with external foundry partners on Multi-Product Wafer (MPW) runs and provide technical design support to customers.
• Contribute to the development of proprietary simulation software and automation scripts to improve reliability prediction.

🧠What You Bring

• Master’s degree with 2+ years of direct industry experience, OR a Bachelor’s degree with 4+ years of experience.
• Must be eligible to obtain a U.S. security clearance due to the nature of defense-related projects.
• Deep knowledge of semiconductor design methodologies and principles.
• Hands-on experience with standard cell design, circuit design, and layout, and associated design tools (e.g. Virtuoso, Spectre, HSPICE)
• Demonstrated experience being involved in test-chip designs and MPW execution.
• Proficiency in design flows including DRC/LVS, timing analysis, and power integrity.
• Extensive experience with simulation tools, specifically for library characterization.

⭐Bonus Points

• Master’s degree with 5+ years of experience, or Bachelor’s with 7+ years in industry.
• Hands‑on design experience with GAA nodes (e.g., Intel 18A), including device architecture and design‑rule familiarity.
• Proven background in SRAM/NVM bitcell design and/or memory compiler development.
• Practical experience with Liberate, PrimeLib, and SiSmart for characterization and modeling.
• Expertise in RHBD for SEE/SEU mitigation, plus proficiency in C++ and scripting (Python/TCL) across advanced nodes (FinFET, GAA, SOI).

💼What You'll Do

• Mentor, manage, and grow a high-performing multidisciplinary team of device physicists, circuit designers, and software engineers.
• Serve as the subject matter expert on Semiconductor Device Physics for radiation effects, including TID, SEE, and SEU.
• Define the technical strategy and roadmap for Radiation Hardened LEAP Standard Cell Libraries across multiple advanced foundry technology nodes.
• Interface regularly with government and DoW customers, DIB customers and strategic partners, and attend relevant conferences. Contribute to BD pipeline assessments and capture tracking. Provide hands-on assistance with technical content of capture proposals and work seamlessly with the contracts and proposal execution teams.
• Direct the development and enhancement of proprietary software tools used for analyzing circuit reliability and radiation-induced error rates.
• Oversee advanced library characterization and simulations to optimize Power, Performance, and Area (PPA) in harsh environments.
• Manage relationships with external foundry partners to influence Multi-Product Wafer (MPW) execution and interface directly with customers to ensure technical quality control.

🧠What You Bring

• Ph.D. in Electrical Engineering, Applied Physics, or a related field with 2+ years of direct industry experience, OR a Master’s degree with 6+ years of direct industry experience, OR a Bachelor’s degree with 8+ years of experience.
• Must be eligible to obtain a U.S. security clearance due to the nature of defense-related projects.
• Deep foundational knowledge of semiconductor device physics and semiconductor design methodologies and principles.
• Hands-on experience with standard cell design, circuit design, and layout, and associated design tools (e.g. Virtuoso, Spectre, HSPICE)
• Demonstrated experience being involved in test-chip designs and MPW execution.
• Proficiency in design flows including DRC/LVS, timing analysis, and power integrity.
• Extensive experience with semiconductor device & design simulation tools, specifically for library characterization.
• Demonstrated track record of managing or leading engineers for a minimum of 5 years.
• Demonstrated end-to-end track record of steering execution of complex technical projects from initial concept/feasibility phase through completion.
• Outstanding communication and presentation skills

⭐Bonus Points

• Ph.D. with 5+ years, Master’s with 9+ years, or Bachelor’s with 10+ years of direct industry experience.
• Proven leadership running and scaling high‑performing multidisciplinary engineering teams while owning technical strategy and roadmaps.
• Demonstrated success shaping government‑focused proposals/contracts and contributing to BD pipelines and strategic captures.
• Direct RHBD experience mitigating SEU/SEE, plus proficiency in C++, Python, and TCL for advanced simulation and automation.
• Hands‑on work with advanced FinFET and GAA nodes (e.g., Intel 18A) and a strong ability to rapidly learn new physics and technology platforms.