About The Role

As a member of our tight knit physical design team, you will be working on the design and analysis of 3D integrated products. This role involves a combination of traditional ASIC/SoC physical design skills, packaging, power, clock and cooling analysis. You will work closely with the architecture and RTL team to do R&D on novel concepts for 3D integration. 

Skills and Qualifications

Required 

•     10+ years of physical design/verification experience. 
•     Strong knowledge of block level and full-chip physical verification methodology. 
•     Expert at optimizing for the best power/performance and area.
•     Experience with the complete physical design flow. Knowledge of Synopsys tool suite is a plus. 
•     Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues. 
•     Expert with IR/EM analysis and resolution.
•     Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements. 
•     Demonstrated ability to work with RTL teams to optimize for physical design.
•     Knowledge of 2.5D or 3D packaging solutions.
•     Must have experience with 3d physical design, 3d die stacking, 3d chip design, die-to-die or wafer-to-wafer.

Preferred    

•     Experience doing full chip floor planning and integration.   
•     Knowledge of clock distribution.
•     Knowledge of cooling analysis.

About The Role

As our team grows Cerebras is looking for a world class physical design engineer. We are looking for a strong learner who can learn how we do PD and integration of our wafer scale design.
As a member of our tight knit physical design team, you will perform a variety of physical design tasks such as synthesis, place and route, timing and block closure / sign off. You will be involved in all aspects of physical design and implementation. You will work closely with the RTL team and with full-chip integration of these blocks.

Skills and Qualifications

• 7+ years of physical design/verification experience.
• Strong experience in block/subsystem timing closure.
• Strong ability to learn and grow with the team.
• Strong knowledge of block level and full-chip physical verification methodology.
• Expert at optimizing for the best power/performance and area.
• Experience with the complete physical design flow. Knowledge of Synopsys tool suite is a plus.
• Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues.
• Expert with IR/EM analysis and resolution.
• Good understanding of full chip floor-planning and integration. 
• Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements.
• Demonstrated ability to work with RTL teams to optimize for physical design.
• Ability to take on a leadership role after ramping up on wafer scale design

The Role:
In this exciting role, you will be responsible for bring up and optimizations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have experience delivering end to end solutions working closely with teams across chip design, system performance, software development and productization.

Responsibilities:

• On Wafer Scale Engines, develop and debug flows that embed well tested and deployable optimizations in production processes to reduce time and costs 
• Work on refining AI Systems across H/W-S/W design constraints such as di/dt, V-F characterization space, current and temperature limits in relation to optimizations for performance.
• Develop/Enhance infrastructure to enable silicon for real world workload testing
• Develop self-checking metrics, as well as instrumentation for debug and coverage
• Work with the silicon architects/designers, performance engineers and software engineers to enhance performance of Wafer Scale Engines.
• Work across domains such as, Software, Design, Verification, Emulation & Validation to refine and optimize performance and process.
• Work with CI/CD tools, git repositories, github, git actions/Jenkins, merge and release flows to streamline test and release.

Skills & Qualifications:

• BS/BE/B.Tech or MS/M.Tech in EE, ECE, CS or equivalent work experience
• 7-10+ years of industry experience
• 3-5 years of experience in Pre-silicon & Post Silicon ASIC hardware
• Good understanding of computer architecture and networking
• Excellent Coding in languages such as Python/Verilog/System Verilog and C
• Proficient in hardware/software codesign and layered architectures.
• Excellent debugging, analytical, and problem-solving skills
• Proficient in large scale testing and automation using pytest and python
• Good presentation skills to refine diverse information and put forth optimization strategies and results.
• Good interpersonal skills, ability & desire to work as a standout colleague
• Proven track record of working cross-functionally learning fast and driving issues to closure 

Preferred:

• Previous work in AI-ML with 100+ CPU core & communication fabric-based design.
• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
• Knowledge of chip defect profiles and mitigation strategies across the hardware and software stack
• Familiarity in creating test and s/w infrastructure at large scale
• Working across global time zones 

Location:
Bangalore, India

Toronto, Canada

Sunnyvale, California.

For Sunnyvale: The base salary range for this position is $175,000 to $275,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

The Role:
In this exciting role, you will be responsible for bring up and optimizations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have experience delivering end to end solutions working closely with teams across chip design, system performance, software development and productization.

Responsibilities:

• On Wafer Scale Engines, develop and debug flows that embed well tested and deployable optimizations in production processes to reduce time and costs 
• Work on refining AI Systems across H/W-S/W design constraints such as di/dt, V-F characterization space, current and temperature limits in relation to optimizations for performance.
• Develop/Enhance infrastructure to enable silicon for real world workload testing
• Develop self-checking metrics, as well as instrumentation for debug and coverage
• Work with the silicon architects/designers, performance engineers and software engineers to enhance performance of Wafer Scale Engines.
• Work across domains such as, Software, Design, Verification, Emulation & Validation to refine and optimize performance and process.
• Work with CI/CD tools, git repositories, github, git actions/Jenkins, merge and release flows to streamline test and release.

Skills & Qualifications:

• BS/BE/B.Tech or MS/M.Tech in EE, ECE, CS or equivalent work experience
• 7-10+ years of industry experience
• 3-5 years of experience in Pre-silicon & Post Silicon ASIC hardware
• Good understanding of computer architecture and networking
• Excellent Coding in languages such as Python/Verilog/System Verilog and C
• Proficient in hardware/software codesign and layered architectures.
• Excellent debugging, analytical, and problem-solving skills
• Proficient in large scale testing and automation using pytest and python
• Good presentation skills to refine diverse information and put forth optimization strategies and results.
• Good interpersonal skills, ability & desire to work as a standout colleague
• Proven track record of working cross-functionally learning fast and driving issues to closure 

Preferred:

• Previous work in AI-ML with 100+ CPU core & communication fabric-based design.
• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
• Knowledge of chip defect profiles and mitigation strategies across the hardware and software stack
• Familiarity in creating test and s/w infrastructure at large scale
• Working across global time zones 

Location:

Sunnyvale, California.

Bangalore, India

Toronto, Canada 

The base salary range for this position is $175,000 to $275,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

The Role: Senior Yield Enhancement Engineer 

We are seeking a highly experienced Senior VLSI Product and Test Engineer with 7+ years of relevant experience in Semiconductor Testing/Failure Analysis/Yield Enhancement. The successful candidate will look at ATE datalogs, understand the defects in detail, disposition wafers based on ATE data and drive FA/Yield enhancement using physical/optical inspection techniques used in FA. 

Suitable candidate will have depth in testing, characterization of silicon defects, failure modes, and experience delivering end-to-end solutions working closely with teams across chip design, fabrication, validation, production, and manufacturing. 

Key Responsibilities  

• Analyze ATE data logs, Shmoo plots, parametric characterization data, and spatial wafer defect patterns. 

• Develop failure analysis tools using optical, photo emission, and laser-based defect localization techniques specific to Cerebras hardware. 

• Develop and execute FIB (Focused Ion Beam) edit plans for Silicon root cause validation. 

• Communicating with OSATs and Fab to drive production testing in HVM environment. 

• Understand DFT strategies including hierarchical scan chains, distributed BIST, SRAM test methodologies, and perform diagnosis on ATE data. 

• Collaborate closely with DFT engineers, silicon architects, designers, performance teams, and software engineers to enhance overall testability and yield 

• Refine test programs across di/dt behavior, voltage-frequency characterization space, current limits, and thermal constraints based on ATE logs and disposition learnings. 

• Understand and write Python scripts and UNIX environment. 

Required Skills & Qualifications 

• Bachelor's or Master's degree in Electrical Engineering / Computer Engineering, or related field 

• 7+ years of hands-on experience in semiconductor test engineering/ FA/ Yield Enhancement. 

• Hands-on experience with lab debug tools including Oscilloscopes (high-speed probing and signal integrity), wafer probe stations, probe cards, Keyence/Optical inspection systems, and advanced imaging techniques. 

• Failure analysis (FA) expertise including use of optical probing tools, physical inspection workflows, and correlation of electrical failures to physical defects. 

• Strong capability to read and understand Digital CMOS layouts, power grids, routing structures and SRAM arrays. 

• ATE test program debugging, and yield improvement experience. 

• Good interpersonal skills with the ability and desire to work as a standout colleague and problem solver. 

• Proven track record of working cross-functionally, learning fast, and driving issues to closure 

• Working knowledge of git repositories, GitHub, git actions/Jenkins, merge and release flows to streamline test and release 

• Proficiency in programming languages: Python, C/C++, Perl for large-scale data analysis 

Preferred Skills 

• Develop fault isolation techniques using OBIRCH/IREM/LADA optical techniques. 

• Experience with advanced test data analysis tools and machine learning techniques for yield optimization. 

• Familiarity with advanced packaging technologies for wafer-scale systems (TSV, advanced interconnects). 

• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking. 

• Knowledge of chip defect profiles and mitigation strategies across manufacturing steps. 

Location 

• North America based. Sunnyvale, up to 20% travel may be needed. 

The base salary range for this position is $175,000 to $250,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Senior IC Design Engineer – IO Signal Integrity & Power Delivery 

About the Role 

In this role, you’ll be at the center of high-speed IO interface design and integration, driving the signal integrity (SI) and power delivery (PI) performance of custom IP within our wafer-scale engine. 

This position emphasizes complete system analysis, architecture, integration and circuit design from transistor level to external voltage regulator, to ensure that custom and third-party IP meets performance, power, and reliability targets across die, 3d assembly, and system level boundaries. 

You’ll collaborate closely with design, packaging, and system engineers to architect and validate custom DDR-like interfaces, IO circuits, and power delivery networks. This is a hands-on technical leadership role for an engineer who understands how circuit behavior, interconnect design, and system integration combine to define product success. 

Key Responsibilities 

• Own IO signal integrity and power delivery analysis for custom and third-party IP integration in full system stack: die level, 3d integration, board level 

• Define interface architecture and design specifications, including signaling schemes, impedance targets, and power distribution requirements. 

• Perform and review channel modeling, IBIS-AMI/SPICE simulations, and system-level SI/PI analysis to ensure timing and margin robustness. 

• Collaborate with internal and external IP providers to evaluate, select, and integrate custom IO and PHY solutions. 

• Lead power delivery network (PDN) modeling and IR-drop analysis, driving improvements across chip, package, and board. 

• Support silicon bring-up, validation, and correlation of simulation results to lab measurements. 

• Provide technical direction on ESD design, IO reliability, and aging (NBTI, PBTI, HCI). 

• Partner with architecture, physical design, and system teams to optimize signal quality, timing closure, and power efficiency. 

• Develop and maintain internal simulation flows, modeling scripts, and automation tools in Tcl/Python. 

Skills & Qualifications 

• 10+ years of experience in IC or IO design, analysis, or integration. 

• Deep understanding of signal integrity, power integrity, and high-speed interface design (DDR, LPDDR, HBM, or similar). 

• Experience with 3d or 2.5d integration, interposers, die stacking 

• Strong knowledge of FinFET CMOS technology and transistor-level device behavior. 

• Expert with HSPICE, FineSim, or equivalent circuit and transient simulation tools. 

• Experience with channel and package modeling, S-parameter extraction, and time/frequency-domain analysis. 

• Proficient in IR-drop analysis, PDN optimization, and decoupling network design. 

• Solid understanding of IO and ESD circuit fundamentals, including protection and clamp strategies. 

• Experience running aging and reliability simulations and applying results to design optimization. 

• Strong scripting and automation experience in Tcl, Python, or similar. 

• Excellent problem-solving, analytical, and cross-functional collaboration skills. 

• B.S. or M.S. in Electrical Engineering or equivalent required (Ph.D. preferred). 

The base salary range for this position is $200,000 to $275,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

About The Role 

Join our close-knit physical design team where you'll excel in synthesizing, placing, and routing high speed designs. Experience the full spectrum of physical design and implementation, collaborating closely with the RTL team and integrating these blocks seamlessly into the full-chip architecture. 

Skills & Qualifications 

• 10+ years of physical design & physical verification experience. 
• Strong knowledge of block level and full-chip physical verification methodology. 
• Strong experience in block/subsystem timing closure.
• Expert at optimizing for the best power/performance and area.
• Experience with the complete physical design flow. Knowledge of Synopsys tool suite is a plus. 
• Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues. 
• Expert with IR/EM analysis and resolution.
• Good understanding of full chip floor planning and integration.   
• Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements. 
• Demonstrated ability to work with RTL teams to optimize for physical design. 
• Knowledge of CPU/GPU design a plus. 
• Skills in Design Compiler, Fusion Compiler, ICC2 or similar physical design tools. 
• BS or MS in Electrical Engineering. 

The salary range for this position is $150,000 – $250,000 annually. Actual compensation will be determined based on factors such as experience, skills, qualifications, and location.

About The Role

• Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
• Managing external ASIC vendor through product development cycle.
• Work closely with PD team members for design closure to meet PPA goals.
• Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
• Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
• Debug silicon-level functional, timing, and power issues during bring up.

• Master’s degree in Computer Science, Electrical Engineering, or equivalent.
• Can work in a hybrid work environment. 
• 8-15 years of experience in delivering complex, high performance high quality RTL designs.
• Experience with Front End Chip integration and third-party IP integration.
• Demonstrated experience in networking, high-performance computing, machine learning or related fields.
• Proven track record of multiple silicon success.
• Experience collaborating and managing external vendors.
• Experience with designing/integrating  high speed IO.
• Networking stack experience including TCP/IP, RDMA and Ethernet.
• Knowledge of PCIe, CPU interfaces and Serdes technology.
• Working knowledge of scripting tools : Python, TCL.

Assets

• Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.

 The base salary range for this position is $175,000 to $275,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Key Responsibilities 

• Work with architects, designers, post-silicon, and software engineers, to ensure a high-quality design that works for silicon. 

• Develop and implement verification strategies, detailed tests, and coverage plans based on micro-architecture. 

• Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage. 

• Implement tests, manage regressions, gather coverage, and debug test failures. 

• Collaborate with cross-functional teams, including architecture, RTL design, physical design, firmware, and validation. 

• Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases. 

• Continuously enhances verification infrastructure and flows to improve efficiency and quality. 

• Contribute to the evolution of the overall verification methodology and best practices across the organization. 

Skills and Qualifications 

• Advanced debugging and problem-solving skills. 

• Deep knowledge of SystemVerilog testbench, DPI, and UVM. 

• Excellent programming skills and knowledge of software engineering practices, including object-oriented design. 

• Experience developing scalable and portable testbenches and components. 

• Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulations. 

• Proficient in scripting languages such as Python or Perl. 

• Good interpersonal skills and the ability to work as a standout colleague are a must. 

• Extremely self-motivated and eager to solve problems 

• 3+ years of Design Verification experience. 

Desired Skills and Qualifications 

• Knowledge of pipelined processor architecture. 

• BS or MS in Computer Science or Electrical Engineering. 

• 3+ years of hands-on Design Verification experience. 

The base salary range for this position is $120,000 to $240,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

We are open to remote candidates.