We are seeking an experienced Senior Engineer - ServiceNow Platform with deep technical expertise in IT Service Management (ITSM), IT Asset Management (ITAM), Platform Integrations, Discovery. The ideal candidate will have proven experience designing, implementing, and managing complex ServiceNow platform solutions. This role will involve overall platform implementation, driving innovation, ensuring system optimization, and responsible for solution design for platform delivery. Ideal candidates demonstrate strong leadership skills to guide technical teams and business stakeholders.

Key Responsibilities:

• Platform Strategy:
• Lead the overall design of the ServiceNow platform, ensuring alignment with business goals and industry and technical best practices.
• Collaborate with business leaders, stakeholders, and technical teams to develop and implement innovative solutions using ServiceNow platform.
• Define platform roadmaps, by ensuring scalability, performance, stability, and audit compliance.
• Lead the design of workflows, integrations, and modules to extend the ServiceNow platform’s capabilities.
• ServiceNow Implementation & Optimization:
• Drive the end-to-end implementation of ServiceNow solutions, focusing on Core foundation, ITSM, ITAM, ITOM, SecOPs, GRC, TPRM, and other relevant modules.
• Manage platform upgrades and ensure all applications are optimized and adhere to enterprise security and compliance standards.
• Provide technical guidance to configure, customize, and develop on the ServiceNow platform based on business needs.
• Manage the documentation of solutions, internal technical and process knowledge base materials, and training of process owners and stakeholders.
• Leadership:
• Provide process governance and technical best practices.
• Providing mentorship and guidance for a team of ServiceNow engineers
• Work closely with cross-functional teams (IT, Security, Engineering, Finance, HR) to drive adoption and ensure platform success.
• The ability to meet strict deadlines and other targets both individually and as the leader of multiple teams, strong decision maker.
• Stakeholder Engagement & Communication:
• Engage with executive leadership and management to understand business objectives, providing solutions that deliver tangible value and measurable outcomes.
• Coordinate with ServiceNow team management to ensure clear communication regarding project status, challenges, and milestones.
• Continuous Improvement:
• Establish technical governance and best practices to continuously improve platform performance and operational efficiency.
• Stay current with the latest ServiceNow trends, releases, and best practices, proactively applying new technologies and functionalities to enhance the platform.
• Create a safe space for engineering team members to experiment with technical solutions that may solve organizational problems.

Required Qualifications:

• Experience:
• 8+ years of experience with ServiceNow, including deep technical expertise in ITSM, ITAM, ITOM, SecOPs, GRC, and TPRM modules.
• Strong experience in architecture and design of ServiceNow platform implementations, including workflows, custom apps, and integrations.
• Proven experience leading technical teams, process governance and delivering large-scale projects.

• Technical Skills:
• Proficiency with scripting languages (JavaScript, Glide, etc.) in the context of ServiceNow platform development and Service Portal (HTML, CSS, AngularJS, SASS, Bootstrap)
• Strong understanding of CMDB, Asset Management, Discovery, Portal, Incident, Problem, and Change Request Management processes.
• Experience integrating ServiceNow with external systems via REST/SOAP APIs, Integration Hub and Spokes.
• Nice to have Perl and Python programming in Linux environment.
• Experience with Agile, Scrum and Kanban development methodologies.

• Leadership & Communication:
• Demonstrated ability to mentor technical teams, ensuring a collaborative and high-performance culture.
• Excellent verbal and written communication skills, with the ability to present complex technical concepts to business leaders and stakeholders.

• Education/Certifications:
• Bachelor's degree in IT, Business, or related field preferred or equivalent work experience.
• ServiceNow Certified Implementation Specialist (ITSM, ITAM, or similar).
• ServiceNow Certified System Administrator (CSA).
• ServiceNow Certified Application Developer (CAD).
• ITIL v3/v4 certification is a plus.
• Certified Technical Architect (CTA) is a big plus.

This position is based in our Reston, VA office and offers a hybrid work schedule.

The pay range is $135,800- $183,800.

The anticipated annual base salary range for this position is noted above, however, base pay offered may vary depending on job-related knowledge, skills, experience. Verisign offers a discretionary bonus which is based on individual and company performance, and certain roles may be eligible for discretionary stock awards.

Role Overview

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions—deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
• 12+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
• 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
• Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
• Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
• Strong scripting ability in Tcl, Python, and/or Perl.
• Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! 

Required Experience

• Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
• Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
• Own floorplanning, macro placement, power grid design, clock tree synthesis, and place-and-route for complex blocks and full-chip designs.
• Drive timing closure at both block and full-chip levels, developing and maintaining timing constraints and signoff methodology.
• Ensure DRC/LVS/EM-IR closure and physical verification sign-off to foundry requirements.
• Integrate hard macros, high-speed SerDes, analog IP, and third-party IP blocks, ensuring seamless physical integration at block boundaries.
• Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
• Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
• Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
• Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
• Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.

Preferred Experience

• Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
• Experience with PCIe, Ethernet, or retimer/signal conditioning ASIC implementation.
• Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
• Hands-on experience with UPF-based multi-voltage/multi-power-domain implementations.
• Familiarity with advanced packaging or multi-die integration and its impact on physical design.
• Experience with ECO methodologies and DFT-aware physical design.
• Knowledge of EMIR-aware implementation techniques and early-stage IR drop mitigation.
• Track record of building and scaling physical design teams through multiple tapeouts.
• Knowledge of agentic AI solutions for EDA automation.

Salary range is CAD $180,000 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

***This job requires active TS/SCI clearance with a CI Polygraph.  Please apply only if you have an active TS/SCI clearance with a CI Polygraph. ***

North Point Technology is hiring a DevOps Engineer to support our Data Centric-Multi-Level Secure (DC-MLS) Enterprise team. This role is ideal for an engineer who thrives in Linux environments, builds reliable automation, and helps deploy and support secure platforms across DC-MLS, HPC, and other mission-driven programs.

Responsibilities:

Build, improve, and maintain DevOps automation processes that support DC-MLS Enterprise deployments and initial site stand-up activities. Develop and manage Linux-based deployment, configuration, and operational workflows across secure environments. Create and maintain automation and scripting solutions to streamline provisioning, support repeatable deployments, and improve platform reliability. Use configuration management and version control tools to manage changes, support releases, and strengthen deployment consistency. Partner with enterprise and core teams to support DC-MLS implementations across HPC and other contract environments.

Required Qualifications:

• Security+ certification
• 5+ years of combined experience in Linux, scripting or software development, and configuration management
• Strong scripting and automation skills in Python, Perl, Korn, Bourne/Bash, Ansible, and other shell scripting tools
• Experience with revision control and source management tools, including CVS, SVN, Git, GitLab, and GitLab CI
• Experience developing and managing DevOps deployment automation processes

Preferred Qualifications:

• Experience supporting secure enterprise deployments in mission-focused environments
• Experience with Linux-based DevOps workflows across HPC or multi-level secure systems
• Experience improving deployment speed, consistency, and operational support through automation

Senior Hardware Engineer

Aliso Viejo, CA

Sony Interactive Entertainment’s Cloud Gaming Engineering and Infrastructure (CGEI) division is leading the Cloud Gaming revolution, putting console-quality video games on any device, from TVs to consoles to mobile devices and beyond.

Our Hardware & Systems Engineering team is looking for a Senior Hardware Engineer to join an innovative team of hardware engineers specialized in custom scale-out computing development. The ideal candidate complements this team and brings technical leadership to team members and partners.

Responsibilities

• Work with local and remote partners to create custom computing hardware by owning the design cycles for scale-out gaming hardware
• Work with external partners and suppliers to design and execute to hardware specifications
• Work with developers in partner software and firmware departments to create system-level solutions that integrate with existing and novel rack-, datacenter, and global-level system architectures.
• End-to-end PCBA design, including schematic- and VHDL-based design and layout oversight
• Hands-on laboratory work, including new hardware bringup and laboratory management

Qualifications

• BSEE required, MSEE or PhD preferred
• 5+ years of proven hardware design and technical leadership
• Experience with Jira and Confluence in both waterfall and Agile environments
• Excellent written and verbal communication skills
• Ability to articulate technical information in a clear and concise manner at all levels, from executive staff to engineers
• Strong cross-team collaboration and interpersonal skills with a variety of roles including engineering, product management, and support
• Strong understanding of digital electrical design
• Deep knowledge of high-speed protocols, including PCIe link and transport, DDR5/6, Ethernet, USB4
• Proven experience with broadly-used electrical design tools
• Experience building, debugging, and troubleshooting novel high-performance hardware systems

 Skills & Knowledge

• Experience with FPGA/CPLD design, including commensurate knowledge of standard and vendor-specific tooling
• Working experience in Perl, TCL, Python, Linux environments and/or C/C++
• Understanding of computer architecture, interconnects, FPGAs and storage technology
• Experience developing test code (firmware, software test code) for prototypes and early validation platforms and commensurate knowledge of integrated development environments (IDEs)
• Experience leading technical work in small workgroups

ENSCO, Inc., Mission Systems Group (MSG) is seeking a RHEL Systems Administrator (Cameo Administrator). In this role the selected candidate will be responsible for monitoring and maintaining the Cameo systems, maintaining the integrity and accessibility of all server resources, hardware, systems, and key processes. They will create and document the framework of technical standards and procedures, and support the engineering team in solutioning, engineering and system administration tasks. The Sys-Admin monitors system health and performance and ensures high availability of the system and helps maintain overall product quality by working closely with the PM and government technical lead to understand and use essential tools for handling files, directories, command-line environments, and documentation.

The Systems Administrator (Cameo Administrator), configures and troubleshoots user profile issues in a virtual desktop environment, monitor and optimize system storage disk on a virtual desktops, and create and deletes user sessions and profiles on a virtual desktop. They are responsible for technical support to a large user community, providing technical expertise in accessing and using the Cameo system, and helps explain technical considerations, environment, and projects to external system partners, and assists with user role management and user support. They will work closely with the information systems security and engineering teams to ensure proper software versioning, scanning and patching of systems, and compliance with ATO/accreditation standards. They are responsible for maintaining a thorough and detailed work product backlog in JIRA, and works closely with PM in communicating project updates and status to senior leadership in Agile ceremonies.

The position is located in Warrenton, VA.

Duties will include:

• Understand, configure and implement systems using Linux command-line in a cloud environment

• Monitor the Cameo systems, maintain the integrity and accessibility of all server resources, hardware, systems, and key processes

• Responsible for configuration and maintenance of Cameo systems within a cloud environment, ensuring high availability of systems and services

• Administer, configure, and troubleshoot user profile issues in a virtual desktop environment

• Monitor and Optimize system storage disk on a virtual desktop

• Create and delete user sessions and profiles on a virtual desktop

• Responsible for user support, user groups and permissions, and user accessibility to system

• Create, maintain and update documentation including SOPs and RunBooks, and maintaining a thorough backlog of work items in an Agile environment

• Responsible maintaining work and change management requests in JIRA

• Assist Information Systems Security and Engineering teams in implementing measures to ensure compliance with security standards

Qualifications Required

• Bachelor's degree or equivalent with a minimum 7 years closely related experience

• Proven experience as a Red Hat Systems Administrator

• Strong knowledge of Red Hat Enterprise Linux (RHEL) command line

• Familiarity with XRDP

• Knowledge of image creation and deployment of a virtual desktop

• Understanding of managing multiple users' sessions or a basic understanding of sessman in a virtual desktop environment

• Knowledge of Cameo NoMagic

• Experience with scripting languages such as Bash, Python, or Perl

• Familiarity with configuration management tools like Ansible or Puppet

• Understanding of networking concepts and protocols

• Excellent problem-solving and troubleshooting skills

• Working knowledge of JIRA

• IAT Level II Certification

• AN ACTIVE DOD TS/SCI CLEARANCE IS REQUIRED FOR THIS POSITION, FOR WHICH YOU MUST BE A U.S. CITIZEN.

Qualifications Desired

• Red Hat Certified System Administrator (RHCSA)

Required Certifications: IAT/IAM Level II Certification
US Citizenship Required: Yes
Security Clearance Required: TS/SCI
Employment Type: Regular Full-time
Background Check Type: 7 Year Pre-Employment
Drug Screen Required: No
Position Contingent Upon Contract Award: No

About INTERACTIVE BROKERS!

This is Hybrid role (4 days in office /1 days remote)

Interactive Brokers Group has been consistently at the forefront of trading innovation, starting with the invention of the first floor-based handheld computer in 1983. We pride ourselves on being primarily a technology company and challenging the status quo. We push boundaries to offer our clients the best trading platform with the most sophisticated features at the lowest cost. Software development is the lifeblood of our firm, and it shows in our stellar brokerage platform. Interactive Brokers is regularly recognized as a leader in the financial services industry.

About your Team:

The Platform engineering team is looking for a Senior Platform Engineer - Design, the person will define, design and develop plans for installation/reconfiguration, and overall management of systems to provide reliable, resilient and secure solutions.

In this role, the person is expected to have strong knowledge of program and scripting, system administration, operating systems, virtualization, networking, engineering, and administration. They have excellent problem-solving skills and systems troubleshooting skills. The person should have passion to continuously improve services, enhance security and optimize service performance.

 What will be your responsibilities within IBKR: 

• Senior Engineer responsible for designing automated solutions leveraging cutting edge tools. Specifically focused on infrastructure and containerization.
• Provides direct support to technical and non-technical entities in order to define requirements and deliver solutions to meet organizational needs including new deployments, upgrades, performance tuning and testing.
• Implement and utilize asset inventory, configuration management database, capacity management, performance management, resource optimization, and security (access control, authorization, and accounting) for all technologies in scope.
• Define requirements, perform research, evaluate vendors/solutions, design/implement solutions, and provide ongoing support for all technologies in scope. Provide simple but effective scalability, performance, and reliability.
• Drive consistent standardized solutions across IB for all hardware, software, configurations, and processes.
• Implement tools and processes for efficient and effective operational management of the environment -- change management, monitoring, alerting, incident handling, customer request handling, etc.
• Schedule and provide after-hours or weekend support when necessary to perform high-risk or planned downtime of IB’s data center systems for upgrades and maintenance.
• Participate in defining and executing on a roadmap of projects that continues to raise the bar through implementing innovative technology, tools, automation, and processes.
• Interact with internal teams to provide solutions and resolve problems in a timely and proactive manner.
• Ability to communicate complex technical concepts to individuals of various technical ability.

What required skill’s you need:

• Programming and Scripting

• Proficiency in languages such as Ansible, Python, or Ruby.

• Scripting skills in Bash, Perl, or similar languages.
• CI/CD Pipelines
•  Experience with continuous integration/continuous deployment tools like Jenkins, GitLab
• Infrastructure as Code (IaC)
• Experience with tools like Terraform, Ansible, Puppet, or Chef.
• Cloud Computing
• Strong knowledge with containerization technologies like Docker and orchestration tools like Kubernetes.
• Familiarity with cloud platforms such as AWS, Google Cloud Platform (GCP), or Azure.
• System Administration
• Strong knowledge of Linux/Unix system administration.
• Experience with system performance tuning and monitoring.
• Networking
• Understanding of TCP/IP, DNS, HTTP/HTTPS, and other network protocols
• Experience with load balancers, firewalls, and VPNs
• Monitoring and Logging
• Proficiency in using monitoring tools such as Prometheus, Grafana, Nagios
• Experience with logging tools like Splunk, Elasticsearch etc..

 To be successful in this position, you will have the following:

• Self-motivated and able to handle tasks with minimal supervision.
• Superb analytical and problem-solving skills.
• Excellent collaboration and communication (Verbal and written) skills.
• Outstanding organizational and time management skills.

Company Benefits & Perks

• Competitive salary, annual performance-based bonus and stock grant
• Retirement plan 401(k) with competitive company match
• Excellent health and wellness benefits, including medical, dental, and vision benefits. Company paid medical healthcare premium.
• Wellness screenings and assessments, health coaches and counseling services through an Employee Assistance Program (EAP)
• Paid time off and a generous parental leave policy
• Daily company lunch allowance provided and a fully stocked kitchen with healthy options for breakfast and snack.
• Corporate events including team outings, dinners, volunteer activities and company sports teams.
• Education reimbursement and learning opportunities.
• Modern offices with multi-monitor setups

Tenstorrent is looking  for a STA methodology engineer who owns timing across advanced-node, high-performance, low-power designs, bringing deep expertise with PrimeTime, noise/crosstalk/OCV analysis, and strong scripting skills. They will lead the development and optimization of end-to-end STA methodologies and flows, drive data- and ML-assisted timing automation, and partner closely with logic, physical design, DFT, and EDA vendors to solve complex timing challenges across multiple IPs and products. 

This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Fort Collins, CO.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

Who you are

• An experienced Static Timing Analysis (STA) / timing methodology engineer with a BS/M in Electrical or Computer Engineering (or equivalent experience) 5+ years in industry, focused on high-performance and low-power designs at advanced technology nodes. As well as a deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
• You are fluent with PrimeTime and related signoff tools (e.g., PT-SI, PTPX, PT-ECO) and have extensive hands-on experience driving signoff correlation, advanced static timing analysis, and signoff closure.
• You are strong at debugging timing constraints, resolving timing correlation issues, and developing effective timing closure strategies.
• You write robust, production-quality scripts in Tcl, Python, and/or Perl and are comfortable building and maintaining CAD utilities and flow components.

What we need

• A senior methodology owner to lead cross-functional efforts to solve complex timing challenges across multiple IPs, projects, and technology nodes. Experience developing and enhancing STA methodologies across the full RTL-to-GDS flow, including: Early timing estimation and timing feasibility checks. Timing optimization techniques in synthesis and place-and-route. Timing signoff methodologies and criteria. Post-route timing ECO strategies and execution.
• A technical leader to architect, optimize, and maintain production STA flows using industry-standard EDA tools, continuously improving PPA (Power, Performance, Area) and runtime efficiency.
• A methodology engineer who can explore and deploy data-driven and ML-assisted techniques to: Improve STA automation. Predict and prioritize timing risk. Guide optimization strategies across blocks and full-chip. Design, implement, and maintain scalable CAD utilities and STA flow components that improve PPA, robustness, and team productivity.
• A methodology owner who continuously refines workflows and introduces new technologies to ensure robust, PPA-optimized timing solutions across all product lines.

What you will learn

• How to scale STA methodologies across a diverse portfolio of IP and SoC programs, balancing aggressive performance targets with strict power and area constraints.
• Best practices for integrating data-driven and ML-assisted approaches into timing flows to improve automation, predictability, and decision-making.
• How to influence tool roadmaps by partnering closely with leading EDA vendors on advanced-node timing, noise, and variability challenges.
• How to operate within and help shape a rapidly evolving startup design environment, including tradeoffs between quick solutions and long-term methodology investments.
• Deeper cross-functional insight into how logic design, physical design, and DFT interact with STA methodology, and how to build flows that serve all of these stakeholders effectively.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

ABOUT THE JOB

Anduril is seeking a Payloads Integration Engineer to join the Maneuver Dominance team at our Costa Mesa HQ. The Maneuver Dominance (MD) Team at Anduril develops aerial robotic systems designed to operate in large coordinated teams in concert with ground maneuver forces. We leverage existing Anduril drone platforms like Ghost, Altius, or Roadrunner, in addition to bringing 3rd party platforms into Anduril’s Lattice ecosystem. We develop perception and autonomy algorithms to solve some of the hardest problems facing our customers.

As a Payload Integration Engineer, you will lead/enable mechanical design, analysis and integration of Anduril payloads into host platforms. This is a unique opportunity to grow your expertise in one of the most challenging and differing engineering domains; large autonomous air vehicles. You will work closely with the program leadership and a wide spectrum of cross-departments as part of a team focused on solving hard problems and changing the industry forever.

WHAT YOU’LL DO:

• Lead or support efforts performing integration, verification and/or validation of weapon systems on Anduril’s Unmanned Aircraft Systems platforms
• Develop program plans, estimates, and schedules
• Develop system/architecture designs, perform system level analysis, and generate requirements
• Troubleshoot conflicting design/development requirements
• Develop and present technical material for reviews and meetings
• Support lab, ground, and flight test events
• Develop/maintain Interface Control Documents, Software Requirement Specifications, Performance Specifications, presentations and review test plans/procedures
• Coordinate and interface with customers, contractors, and engineering groups assigned to projects
• Support ongoing operation of the weapons systems
• Provide support for proposals/white papers for future efforts or capabilities
• Provide direction to design and to technical staff

REQUIRED QUALIFICATIONS

• Bachelor’s degree, Master’s degree or PhD in engineering, computer science or a related technical discipline from an accredited institution and progressive engineering experience as follows; nine or more years of experience with a bachelor’s degree, seven or more years of experience with a master’s degree or five or more years with a PhD. May substitute equivalent engineering experience in lieu of education.
• Software programming or embedded systems experience (familiarity with C++, MATLAB, Python, PERL scripting, etc.)
• Familiarity with Air-to-Air weapons, MIL-STD-1553, and logical Interface Control Documents
• Experience integrating weapons, payloads, or avionics onto aircraft
• Experience with weapon or tactical datalinks
• Must be customer focused with the ability to formulate and implement plans to resolve technical engineering problems
• Ability to travel to support program and test events (up to 25%)
• Must be eligible to obtain and maintain a U.S. TS clearance

PREFERRED QUALIFICATIONS

• Experience in NX/Teamcenter
• Experience in Solidworks
• Experience designing mechanical parts and test equipment (CAD).
• Understanding of manufacturing methods (machining, sheet metal, composites, 3D printing, injection molding, composite lamination, etc)
• Experience developing subsystem layouts, performing architectural trade studies, and evaluating vendor performance data

What You’ll Do

We are looking for a passionate and experienced Staff Engineer, SRAM Layout to lead the development of next-generation SRAM solutions.

• Lead the development and execution of full-custom SRAM memory layout and sign-off verification flows (including compiler automation where applicable).
• Collaborate closely with circuit designers to translate schematics into efficient, high-performance physical layouts, own floor planning, placement, routing, and tape-out.
• Design and optimize SRAM layouts at the cell, array, and peripheral levels for area, speed, power, yield, and manufacturability.
• Perform and close all physical verification; DRC, LVS, ERC, antenna checks, custom memory rules, RC extraction, parasitic analysis, and signal integrity verification.
• Debug and resolve layout issues efficiently, including process-specific challenges in advanced nodes.
• Lead layout reviews, mentor junior engineers, and drive best practices, optimization techniques, design-rule compliance, and knowledge sharing.
• Develop automation scripts (Perl, Tcl, SKILL, etc.) to improve productivity.
• Address reliability concerns such as EM/IR drop, soft errors, and process variability. 
• Work cross-functionally with circuit, architecture, verification, and foundry/process teams to ensure first-pass silicon success and support product integration

What You Bring

• Bachelor's degree with 10+ years of experience in custom SRAM, memory compiler and IC physical layout design or master's degree 8+ years of experience strongly preferred. 
• 3 year’s experience in leadership of management role preferred.
• Extensive experience in SRAM layout design in advanced process nodes (e.g., 3nm, 2nm, or below).
• Demonstrated ability to lead, mentor, and manage a team of layout engineers. 
• Strong project management skills to handle complex schedules and cross-functional collaboration. 
• Strong proficiency with industry-standard EDA tools: 
• Candence Virtuoso (or Custom Compiler/IC Compiler) for custom/analog layout. 
• Physical verification tools for DRC/LVS/ERC flows. 
• Perform and close all physical verification; DRC, LVS, ERC, antenna checks, custom memory rules, RC extraction, parasitic analysis, and signal integrity verification. 
• Experience with RC extraction, parasitic reduction, and memory-specific verification. 
• Scripting/automation skills (Perl, Tcl, SKILL, etc.) are highly valued. 
• Proven ability to drive layout quality, constraints, and closure while collaborating in global, cross -functional teams. 
• Prior work on high-speed, low-power SRAM in leading-edge nodes preferred. 
• Mentoring or technical leadership experience preferred. 
• Understanding of SRAM architecture, timing, power analysis, and yield optimization preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-SF1

What You’ll Do

We are looking for a passionate and experienced Staff Engineer, SRAM Circuit Design  to lead the development of next-generation SRAM solutions. In this position, you will drive end-to-end design of high-performance, low-power memory circuits used in cutting-edge semiconductor products. Your work will directly influence the power, performance, and area (PPA) efficiency of future computing, mobile, and AI platforms.

This role combines deep technical expertise with strategic team leadership, offering the opportunity to innovate at the forefront of semiconductor design.

• Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm).
• Optimize SRAM designs for performance, power and area (PPA) and yield.
• Develop custom layouts and perform physical design verifications (e.g., DRC, LVS).
• Evaluate trade-offs between speed, power, and area to meet design targets.
• Develop and improve SRAM design methodologies, including automation scripts for design, simulation, and verification.
• Work with product and test engineers to develop test plans and support silicon bring-up.
• Mentor Junior engineers, providing guidance on SRAM design techniques and best practices.
• Perform extensive circuit simulations using tools like HSPICE, finesim or cadence Spectre to validate SRAM functionality and performance.
• Contribute to patents, technical papers, or industry conferences to advance SRAM technology.

What You Bring

• Bachelor's degree in electrical engineering with 10+ years of industry experience or master's degree in electrical engineering with 8+ years of experience strongly preferred. 
•  Prior experience in SRAM or memory circuit design, with a proven track record of delivering SRAM designs in advanced process nodes.
• Strong understanding of semiconductor devices physics and process technology (FinFET, GAA, SOI, etc.).
• Expertise in SRAM architecture, including bitcells, sense amplifiers, write drivers, and read/write control paths.
• Familiarity with timing analysis, power analysis, and design for manufacturability (DFM).
• Proficiency in circuit simulation, variation analysis, and design tools such as Spectre, HSPICE, Cadence Virtuoso, etc.
• Knowledge of scripting languages (e.g., Python, Perl, TCL) for automation of design tasks.
• Strong cross-functional collaboration and communication skills for working with design, layout, verification, and technology development teams.
• Experience with advanced technology nodes (e.g., 5nm, 3nm, or beyond).
• Knowledge of SRAM compiler development and experience with low-power SRAM design techniques (e.g., power gating, voltage scaling).
• Background in silicon debug and root-cause analysis.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change. 

#LI-SF1

Memory IO Lab is part of Samsung’s Memory Business Unit, the industry's all-time DRAM and NAND Flash leader both in technology as well as in volume. Memory IO’s vision is to provide memory interface technology solutions which can be adopted in DDR, LPDDR, GDDR, and more. We are an integral part of Samsung’s paramount R&D innovation engine. We work closely with cross-disciplinary development teams to bring feature innovation to product roadmaps.

Come and join the team that is providing the next generation IO tech solutions to support emerging machine learning applications, data analytics, and edge computing.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy

What You'll Do

• Hands on in analog circuit design, which includes circuit design, running simulations to confirm functionality and performance, and work with verification team to verify design. The mixed-signal designs will include but are not limited to the following: high-speed data converters, PLL, and SERDES.
• Guide layout floor-planning block and top level to optimize the overall performance; supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary.
• Ownership of circuit and system specifications.
• Simulate designs with state-of-the-art CAD tools.
• Document designs and simulation results.

What You Bring

• BS 10+ years experience, MS 8+years of experience, PhD 5+ years experience in Electrical Engineering, Computer Science preferred. 
• 5+ years of experience working with system on chip architecture, high-speed serial interfaces, analog and mixed-signal circuit designs using advanced CMOS technology nodes.
• Prior experience in design of any one of the standard high speed interfaces like DDR, LPDDR, , GDDR, HBM I/O interface.
• Needs to be an expert in providing and understanding layout requirements of high speed circuits.
• Knowledge of all facets of high speed I/O design but specifically should include DLL / PLL / FFE / CTLE / DFE, output drivers , ODT, Duty cycle correction (DCC), Training/calibration to improve timing, high speed power design and low power design.
• Experience working closely with device/process team to define transistor specs
• The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment.
• Ability to troubleshoot and analyze complex problems.
• Excellent communication (written and verbal) and interpersonal skills
• Experience in high frequency clock distribution design, implementation, and analysis.
• Deep understanding of PPA (performance, power, and area) trade-offs.
• Ability to handle EDA tools well, such as Cadence, MATLAB (Simulink), and EM tools
• Experience on silicon bring-up and automatic measurement using script
• Strong scripting and automation skills using Tcl/Perl. Knowledge of Python is a plus.
• Self-motivated problem-solver with an ability to work well in a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. 

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

At the Technology Enabling Development Lab (TED), our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

We are looking for a dynamic, self-motivated, experienced engineer to architect and lead functional test coverage and test methodologies for NVMe SSDs.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Manage Enterprise server infrastructure, execute Customer Qual tests and debug failures
• Execution of enterprise SSD qualifications in customer systems.
• Communicate with team lead to understand qualification processes and test plans. Report status of qualifications and manage customer expectations.
• Coordinate  with internal team and customer test engineers to execute qual plans as per schedule. Teams will be both local and remote.
• Triage test failures and do a first level FA. Design and execute experiments to root cause defects and verify fixes in coordination with development teams.
• Provide feedback to functional test teams on issues seen in customer quals to better functional test coverage.
• Contribute in Triaging customer field issues and provide support for timely resolution of customer issues.
• Identify automation opportunities and help Automation team to continue to improve and add to the existing framework.

What You Bring

• BS in Computer Science or related technical field with 10+ years of system level testing or development of enterprise servers and enterprise storage systems experience or MS with 8+ years preferred.
• Experience with at least storage protocol like NVMe/PCIe, SAS, SATA, Fibre Channel
• Familiar with one of protocol analyzers like LeCroy, SerialTek, or Xgig System or device level performance analysis
• Proficiency in server operating systems especially system debug tools such as system logs.
• Knowledge of enterprise storage/server system technologies.
• Expertise in storage test tools such as performance benchmarks, IO stress tools, protocol certifications, Test execution and bug management tools.
• Scripting experience such as in Perl, Shell or Python
• Experience with SSD or HDD testing
• NetApp/HPE/Dell/IBM System Experience
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

The SoC Architect will serve as a key technical leader, translating client requirements into an optimal SoC blueprint that achieves aggressive PPA (Power, Performance, Area) targets and driving its successful implementation.  This role will be a critical leader who provides the technical blueprint that ultimately realizes our clients' business objectives and should have a deep understanding of the complexities of custom SoC development and the ability to leverage broad system knowledge to create innovative solutions.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy with an average of 20% travel per month.

Reports to: Team leader/Head of Custom SoC Solutions Team

What You’ll Do

Customer Requirement Definition and Architecture Design:

• Analyze and define the functional, performance, and power requirements based on the client's end product and application (e.g., mobile, edge device, data center or physical AI).
• Conceive and specify the Top-Level SoC Architecture and Microarchitecture, including CPU/GPU/NPU cores, memory subsystem, Interconnect (Coherent/Non-Coherent Fabric), and high-speed I/O interfaces (e.g., PCIe, UALink or ESUN).

Architecture Exploration and Validation:

• Evaluate various architectural trade-offs and validate architectural decisions using performance and power modeling (C/C++, SystemC).
• Provide technical guidance on IP selection, integration, and system optimization, and define the Design for Debug/Test/Excellence (DFx) strategy.

Technical Collaboration and Leadership:

• Collaborate closely with cross-functional teams (HW Design, Verification, Physical Design, Software) to ensure architectural specifications are accurately translated into the design and implementation phases.
• Identify and resolve technical risks throughout the project lifecycle, and lead technical communication with clients and

 What You Bring

• Bachelor’s Degree in Electrical Engineering, Computer Science, or related discipline and 10+ years of experience, or Master’s and 8+ years of experience. 
• 5+ years experience in SoC Architecture or System Engineering (experience in custom ASIC/SoC projects is a plus)
• Deep understanding of Computer Architecture and SoC Design (including CPU, GPU, Accelerators, Caches, and Memory Systems).
• Expert knowledge and design experience with on-chip interconnects (e.g., AMBA AXI/CHI) and High-Speed Interface protocols.
• In-depth knowledge of Power Management and low-power design techniques.
• Experience with SoC-level Clock, Reset, and Power Domain architecture.
• Comprehensive understanding of the overall RTL design and SoC design flow (Implementation & Verification).
• Excellent problem-solving skills to independently identify, analyze, and resolve complex technical issues.
• Ability to communicate and negotiate effectively with diverse stakeholders, including hardware and software engineering teams, managements, and clients.
• Proficiency in scripting languages such as Python/Perl
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD's with 10+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

The Technology Enabling Development Lab (TED) Our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Design and development of high performance firmware and software for cutting-edge enterprise SSD products.
• Debug, optimize, and validate SSD firmware on complex embedded multi-core architectures.
• Support customer qualification and adoption of SSD products.
• Participate in ground-breaking advanced SSD storage development and research projects.

What You Bring

• BS in Computer/Electrical Engineering or Computer Science with 3+ years of working experiences in silicon development or MS in Computer/Electrical Engineering or Computer Science with 1+ years of relevant working experience or PhD and 0+ years of relevant experience in storage firmware development is required.
• Strong programming experience and demonstrated proficiency in C/C++ for embedded systems, including development of algorithms, manipulation of complex data structures, and implementing highly optimized code, is required.
• Relevant hands on experience in embedded software or firmware development, including storage devices or other embedded platforms is required.
• Experience with one or more of the following storage related technologies: NVM Express, PCI Express, SAS, SCSI, NAND Flash/FTL, Fibre Channel, SATA, eMMC, or UFS is beneficial.
• Experience with ARM or equivalent embedded multi-core microprocessor architectures is required.
• Hands on experience with JTAG/ICE debuggers and protocol analyzers is required.
• Some scripting experience in one of Python/Perl/Javascript is desired.
• Familiarity and experience with modern agile software development methodologies and practices is preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-SF1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Responsibilities and Description: 

The Physical Design and Verification Engineer will be responsible for RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification. 

Required Qualifications: 

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
• Minimum 5 years of experience in digital physical design and verification.
• Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff.
• Deep knowledge on industry standards and practices in physical design including physically-aware synthesis flow, floor-planning, and place & route, metal fill, chip finishing, signal integrity checks, and dynamic EMIR-Drop analysis, and formal ESD verification.
• Experience in Signoff ECO flow to fix timing, noise, IR-Drop and EMIR violations.
• Experience in physical design verification to debug LVS/DRC/PERC issues at the chip/block level using industry standard tools.
• Experience in developing automation flow and scripts using Python, Perl, Makefile, Tcl and UNIX shell.

Preferred Qualifications: 

• Master of Science (M.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
• Experience working on physical design and implementation of complex ASIC systems at advanced technology nodes, preferably 16nm and below. 
• Experience in DFT (Design For Test) flows and ATPG.
• Experience in I/O design flow in multi-voltage power domain.
• Experience in building chip floor-plan including pin placement, partitions and power grid.
• Experience in hierarchical synthesis, place-and-route and design closure to meet timing, area, and UPF-driven low power constraints.
• Experience with build tools such as CMake and Bazel.
• Experience with code coverage and regression setup.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

Position Description:

The Services PreSales Architect is a technical authority on both cloud and on-premises based IAM systems and is responsible for ensuring the successful design and implementation of Okta’s & Auth0’s industry leading cloud identity platform for our customers. Your main focus will be on driving the success of Okta's and Auth0's identity offerings. You will cultivate strong, trusted partnerships with customers, concentrating on their success and helping them achieve their business goals by promoting innovative and creative solutions. A key part of your role is to translate customer business needs and insights into a clear, actionable strategy that the delivery team can execute to help customers achieve tangible results and high business value from their initiatives. This is a key member of the Professional Services (PS) Pre-Sales team.

Job Duties and Responsibilities:

• Lead the pre-sales discovery of functional and technical requirements required to establish an Identity platform for our customers. 
• Lead Partners, Customers and Engagement Managers to document and mitigate technical risk identified during discovery.
• Create estimates to implement the proposed solution.
• Review services estimates to ensure project scope can be successfully delivered as outlined - technical risk is appropriately mitigated and timelines follow staffing guidelines.
• Lead and develop co-delivery proposals by identifying and engaging appropriate partners.
• Drive New Product Introduction (NPI) across PS by training Engagement Managers and developing associated assets such as scope modules, SKUs, success stories and enablement toolkits.

Minimum REQUIRED Knowledge, Skills, and Abilities:

• 10+ years of overall IT / software development experience, solution design and technical architecture experience
• 5+ years of Okta implementation experience
• 5+ years of consulting experience
• 5+ years driving application architecture design
• 5+ years of experience with (IAM) architectures
• Experience with employee and customer identity use cases: HR driven identity, Active Directory, SSO, SaaS application integrations.
• Experience with Identity Governance and Privileged Access Management use cases. 
• Demonstrated ability to work and interact with high-level customer executives and technical resources.
• Experience in leading discovery workshops to derive customer requirements and specifications.
• Experience in developing functional specifications and system design specifications for customer engagements.
• Strong knowledge of Security Architecture, Design and Operations, LDAP, Active Directory, SSO, SAML, OIDC, RBAC, OAuth, JSON, REST.
• Experience integrating with a multitude of On-Prem and SaaS based products.
• Exhibits confidence and a deep understanding of emerging industry practices when solving business problems.
• Identifies critical issues with ease.
• Effectively communicates technical information to non-technical audiences.
• Manages customer expectations effectively.
• Application design experience.
• Clear and Dynamic Communication.
• Ability to travel up to 50%

Highly Desirable Knowledge, Skills, and Abilities:

• Knowledge of software development security and cryptography.
• Familiarity with IAM solution providers.
• Experience with API Gateways, CASB, and Reverse Proxies (NGINX)
• Proficiency with various open-source software and development tools
• Proficiency in one or more of the following: .Net, Ruby, Java, Python or Perl

Education and Certification

• A Bachelor’s degree (or equivalent) in Computer Science, Information Technology or related discipline required.
• Okta Certified Technical Architect or a combination of Okta Certified Consultant and Okta Certified Developer is a plus.
• CISSP certification is a plus.
• TOGAF certification is a plus.

#LI-BF1

#LI-Hybrid

P10902_3357735

The Role 

We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
• Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
• Participate in ASIC team interviews.
• Drive advancement of DV methodologies and improvements.
• Manage external IP providers and verification partners when needed.
• Take lead on large and/or complex systems. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
• Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
• Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
• Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
• Experience with developing and integrating reference models.
• Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
• Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
• Involvement in post-silicon validation planning and execution. 

Nice to Have

• Experience with low power verification.
• Experience with analog behavioral models.
• Familiarity with physical design flows.
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

• Base salary range for this role is $190,000 – $285,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews and microarchitecture discussions. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
• Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
• Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
• Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git). 

Nice to Have

• Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management.
• Familiarity with developing and integrating reference models.
• Understanding of RTL design flows and some industry standard interfaces (ex: APB/AHB/AXI).
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

• Base salary range for this role is $130,000 – $200,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
• Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
• Participate in ASIC team interviews.
• Contribute to advancement of DV methodologies and improvements.
• Engage external IP providers and verification partners when needed. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
• Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).
• Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
• Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
• Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).
• Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++). 

Nice to Have

• Experience with developing and integrating reference models.
• Understanding of low power verification.
• Familiarity with gate-level simulation and analog behavioral models.
• Involvement in post-silicon validation planning and execution.
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 
  

Compensation and Benefits:

• Base salary range for this role is $170,000 – $250,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

ABOUT THE TEAM 

Anduril Intelligence Systems (AIS) is focused on positioning Anduril as a lead provider of specialized engineering and products for Intelligence Community (IC) customers. We work within the IC to understand their requirements, shape their concepts of operation, and deliver exquisite capability across their problem set. We aim to develop and deploy critically needed capabilities that address our customers’ most pressing national security requirements.

ABOUT THE JOB

We are looking for an Senior Electrical Test Design Engineer to join our rapidly growing team in Reston, Virginia. You will deliver test systems for Anduril’s electronic products. As a strong Test Automation Engineer you will need to have a proven track record of delivering turn key test solution for electronic components and systems and has a background in hardware, software, integration and sustainment. This person will work with the rest of the organization to identify gaps in test coverage and own the design and delivery of the hardware and software test solution. Anduril develops test systems used to ensure the quality and reliability of our aerial and ground based systems. The team works on air vehicles such as Roadrunner, Ghost, Anvil and Fury and develop complex manufacturing test solutions to our internal manufacturing team or contract manufacturers. We work closely and cross-functionally with the rest of our Product Engineering groups that include Electrical, Mechanical and Firmware Engineering to solve and improve our manufacturing process, product quality and reliability.

REQUIRED QUALIFICATIONS

• Bachelor’s Degree or Master’s Degree in Electrical Engineer or equivalent
• 5+ years of experience designing functional test equipment and PCBAs
• Experience in Schematic Capture and PCBA layout
• Working knowledge of scripting language to develop automation. Python, Matlab, PERL, Labview or SHELL
• Understanding of peripherals and developing test and validation strategies
• Experience with computer hardware communication bus protocols: USB, I2C, I2S, CSI, Ethernet, SPI, PCIe, HDMI, CAN, etc
• Understanding of memory hierarchy and developing test and validation strategy
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase
• Collaborate with a cross-functional team to support product development from prototype to production
• Currently possesses and is able to maintain an active U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• Master’s Degree in Electrical Engineering or equivalent
• Proficiency in MS Word, Excel, PowerPoint and VISIO
• A detail-oriented individual who strives in an environment that values effective team collaboration
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase

ABOUT THE TEAM

Anduril Intelligence Systems (AIS) is focused on positioning Anduril as a lead provider of specialized engineering and products for Intelligence Community (IC) customers. We work within the IC to understand their requirements, shape their concepts of operation, and deliver exquisite capability across their problem set. We aim to develop and deploy critically needed capabilities that address our customers’ most pressing national security requirements.

ABOUT THE JOB

We are looking for an Electrical Test Design Engineer to join our rapidly growing team in Reston, Virginia. You will deliver test systems for Anduril’s electronic products. As a strong Test Automation Engineer you will need to have a proven track record of delivering turn key test solution for electronic components and systems and has a background in hardware, software, integration and sustainment. This person will work with the rest of the organization to identify gaps in test coverage and own the design and delivery of the hardware and software test solution. Anduril develops test systems used to ensure the quality and reliability of our aerial and ground based systems. The team works on air vehicles such as Roadrunner, Ghost, Anvil and Fury and develop complex manufacturing test solutions to our internal manufacturing team or contract manufacturers. We work closely and cross-functionally with the rest of our Product Engineering groups that include Electrical, Mechanical and Firmware Engineering to solve and improve our manufacturing process, product quality and reliability.

REQUIRED QUALIFICATIONS

• Bachelor’s Degree or Master’s Degree in Electrical Engineer or equivalent.
• 5+ years of experience designing functional test equipment and PCBAs.
• Experience in Schematic Capture and PCBA layout.
• Working knowledge of scripting language to develop automation. Python, Matlab, PERL, Labview or SHELL.
• Understanding of peripherals and developing test and validation strategies.
• Experience with computer hardware communication bus protocols: USB, I2C, I2S, CSI, Ethernet, SPI, PCIe, HDMI, CAN, etc.
• Understanding of memory hierarchy and developing test and validation strategy.
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase.
• Collaborate with a cross-functional team to support product development from prototype to production.
• Currently possesses and is able to maintain an active U.S. Secret security clearance.

PREFERRED QUALIFICATIONS

• Master’s Degree in Electrical Engineering or equivalent.
• A detail-oriented individual who strives in an environment that values effective team collaboration.
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase.

ABOUT THE TEAM

Anduril’s Tactical Recon & Strike (TRS) is a division with two missions: 1) build highly capable autonomous drones, and 2) build solid rocket motors at scale. We transform products like Ghost, Anvil, Bolt, and Altius from early concepts into fully operational capabilities by partnering closely with specialist engineering, operations, and production teams. Through our Anduril Rocket Motor Systems (RMS) team, we design and manufacture solid rocket motors using advanced materials, proprietary formulations, and high-volume production methods—delivering safe, reliable propulsion systems that support a wide range of mission requirements. TRS hires software engineers & hardware engineers, who are excited to build across a diverse and powerful portfolio—from autonomous aerial systems to high-performance solid rocket motors. Our teams contribute to highly capable autonomous robotics systems and propulsion products that operate reliably in the most demanding mission environment.

The Electrical Test Engineering team at Anduril develops test systems used to ensure the quality and reliability of our aerial and ground based systems. The team works on air vehicles such as the ALTIUS and develop complex manufacturing test solutions to our internal manufacturing team or contract manufacturers. We work closely and cross-functionally with the rest of our Product Engineering groups that include Electrical, Mechanical and Firmware Engineering to solve and improve our manufacturing process, product quality and reliability.

ABOUT THE JOB

We are looking to bring on a Senior Electrical Test Engineer to design and deliver test systems for Anduril’s electronic products. This person will work with the test of the organization to identify gaps in test coverage and own the design and delivery of the hardware and software test solution. A strong Senior Electrical Test Engineer will need to have a proven track record of delivering turn key test solution for electronic components and systems and has a background in hardware, software, integration and sustainment.

WHAT YOU'LL DO

• Lead and own Hardware Qualification test plan definition for new products and new features, in collaboration with firmware, software, and hardware design teams
• Determine test strategies that optimize product safety, product reliability, risk mitigation, FMEA coverage, and schedule
• Design and execution of PCBA and electrical system components with hands on testing and rework as necessary
• Data analysis and clear communication of results and collaboration with design engineers to resolve any product problems found via test
• Design and implement next generation test automation hardware systems to facilitate fast and repeatable testing of product
• Manage purchasing, build, integration and final commissioning of functional testers
• Develop test procedures and test automation from component level to system level
• Support board bring-up and bench validation as needed
• Support Design Engineer with DFT, provide feedback from test results to improve quality and test coverage
• Support manufacture test bring-up and yield
• Support quality field failure analysis
• Familiarity with measurement analysis techniques such as Gage RR and Process Capability Analysis

REQUIRED QUALIFICATIONS

• Bachelor’s Degree or Master’s Degree in Electrical Engineer or equivalent
• 8+ years of experience designing functional test equipment and PCBAs
• Experience in Schematic Capture and PCBA layout.
• Knowledge of scripting language to develop automation. Python, Matlab, PERL or SHELL. Experience in LabVIEW is a plus
• Instrument control using VISA and SCPI
• Understanding of peripherals and developing test and validation strategies
• Experience with computer hardware communication bus protocols: USB, I2C, I2S, CSI, Ethernet, SPI, PCIe, HDMI, CAN, etc
• Understanding of memory hierarchy and developing test and validation strategy
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase
• Collaborate with a cross-functional team to support product development from prototype to production
• Experience with hands-on electrical engineering work

PREFERRED QUALIFICATIONS

• Understanding both hardware and software integration and test process
• Advance proficiency in MS Word, Excel, PowerPoint and VISIO
• Understanding of lab safety protocols when working in all types of lab environment
• A detail-oriented individual who strives in an environment that values effective team collaboration
• Self-motivated: Demonstrate ability to set direction and proactively identify and fills gaps where needed

ABOUT THE TEAM

Anduril’s Tactical Recon & Strike (TRS) is a division with two missions: 1) build highly capable autonomous drones, and 2) build solid rocket motors at scale. We transform products like Ghost, Anvil, Bolt, and Altius from early concepts into fully operational capabilities by partnering closely with specialist engineering, operations, and production teams. Through our Anduril Rocket Motor Systems (RMS) team, we design and manufacture solid rocket motors using advanced materials, proprietary formulations, and high-volume production methods—delivering safe, reliable propulsion systems that support a wide range of mission requirements. TRS hires software engineers & hardware engineers, who are excited to build across a diverse and powerful portfolio—from autonomous aerial systems to high-performance solid rocket motors. Our teams contribute to highly capable autonomous robotics systems and propulsion products that operate reliably in the most demanding mission environment.

ABOUT THE JOB

We are looking to bring on a Electrical Test Engineer to design and deliver test systems for Anduril’s electronic products. This person will work with the test of the organization to identify gaps in test coverage and own the design and delivery of the hardware and software test solution.

WHAT YOU'LL DO

• Work on a Electrical Test Engineering team that owns/defines for new products and new features, in collaboration with firmware, software, and hardware design teams
• Determine test strategies that optimize product safety, product reliability, risk mitigation, FMEA coverage, and schedule
• Design and execution of PCBA and electrical system components with hands on testing and rework as necessary
• Data analysis and clear communication of results and collaboration with design engineers to resolve any product problems found via test
• Design and implement next generation test automation hardware systems to facilitate fast and repeatable testing of product
• Manage purchasing, build, integration and final commissioning of functional testers
• Develop test procedures and test automation from component level to system level
• Support board bring-up and bench validation as needed
• Support Design Engineer with DFT, provide feedback from test results to improve quality and test coverage
• Support manufacture test bring-up and yield
• Support quality field failure analysis
• Familiarity with measurement analysis techniques such as Gage RR and Process Capability Analysis

REQUIRED QUALIFICATIONS

• Bachelor’s Degree or Master’s Degree in Electrical Engineer or equivalent
• 3+ years of experience designing functional test equipment and PCBAs
• Experience in Schematic Capture and PCBA layout.
• Knowledge of scripting language to develop automation. Python, Matlab, PERL or SHELL. (Experience in LabVIEW is a value, but less required)
• Instrument control using VISA and SCPI
• Understanding of peripherals and developing test and validation strategies
• Experience with computer hardware communication bus protocols: USB, I2C, I2S, CSI, Ethernet, SPI, PCIe, HDMI, CAN, etc
• Understanding of memory hierarchy and developing test and validation strategy
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase
• Collaborate with a cross-functional team to support product development from prototype to production
• Experience with hands-on electrical engineering work

PREFERRED QUALIFICATIONS

• NI TestStand experience
• Understanding both hardware and software integration and test process
• Advance proficiency in MS Word, Excel, PowerPoint and VISIO
• Understanding of lab safety protocols when working in all types of lab environment
• A detail-oriented individual who strives in an environment that values effective team collaboration
• Self-motivated: Demonstrate ability to set direction and proactively identify and fills gaps where needed

ABOUT THE TEAM 

Anduril Intelligence Systems (AIS) is focused on positioning Anduril as a lead provider of specialized engineering and products for Intelligence Community (IC) customers. We work within the IC to understand their requirements, shape their concepts of operation, and deliver exquisite capability across their problem set. We aim to develop and deploy critically needed capabilities that address our customers’ most pressing national security requirements.

ABOUT THE JOB

We are looking for an Senior Electrical Test Design Engineer to join our rapidly growing team in Santa Ana, CA. You will deliver test systems for Anduril’s electronic products. As a strong Test Automation Engineer you will need to have a proven track record of delivering turn key test solution for electronic components and systems and has a background in hardware, software, integration and sustainment. This person will work with the rest of the organization to identify gaps in test coverage and own the design and delivery of the hardware and software test solution. Anduril develops test systems used to ensure the quality and reliability of our aerial and ground based systems. The team works on air vehicles such as Roadrunner, Ghost, Anvil and Fury and develop complex manufacturing test solutions to our internal manufacturing team or contract manufacturers. We work closely and cross-functionally with the rest of our Product Engineering groups that include Electrical, Mechanical and Firmware Engineering to solve and improve our manufacturing process, product quality and reliability.

REQUIRED QUALIFICATIONS

• Bachelor’s Degree or Master’s Degree in Electrical Engineer or equivalent
• 5+ years of experience designing functional test equipment and PCBAs
• Experience in Schematic Capture and PCBA layout
• Working knowledge of scripting language to develop automation. Python, Matlab, PERL, Labview or SHELL
• Understanding of peripherals and developing test and validation strategies
• Experience with computer hardware communication bus protocols: USB, I2C, I2S, CSI, Ethernet, SPI, PCIe, HDMI, CAN, etc
• Understanding of memory hierarchy and developing test and validation strategy
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase
• Collaborate with a cross-functional team to support product development from prototype to production
• Currently possesses and is able to maintain an active U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• Master’s Degree in Electrical Engineering or equivalent
• Proficiency in MS Word, Excel, PowerPoint and VISIO
• A detail-oriented individual who strives in an environment that values effective team collaboration
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase

ABOUT THE TEAM

Anduril Intelligence Systems (AIS) is focused on positioning Anduril as a lead provider of specialized engineering and products for Intelligence Community (IC) customers. We work within the IC to understand their requirements, shape their concepts of operation, and deliver exquisite capability across their problem set. We aim to develop and deploy critically needed capabilities that address our customers’ most pressing national security requirements.

ABOUT THE JOB

We are looking for an Electrical Test Design Engineer to join our rapidly growing team in Reston, Virginia. You will deliver test systems for Anduril’s electronic products. As a strong Test Automation Engineer you will need to have a proven track record of delivering turn key test solution for electronic components and systems and has a background in hardware, software, integration and sustainment. This person will work with the rest of the organization to identify gaps in test coverage and own the design and delivery of the hardware and software test solution. Anduril develops test systems used to ensure the quality and reliability of our aerial and ground based systems. The team works on air vehicles such as Roadrunner, Ghost, Anvil and Fury and develop complex manufacturing test solutions to our internal manufacturing team or contract manufacturers. We work closely and cross-functionally with the rest of our Product Engineering groups that include Electrical, Mechanical and Firmware Engineering to solve and improve our manufacturing process, product quality and reliability.

REQUIRED QUALIFICATIONS

• Bachelor’s Degree or Master’s Degree in Electrical Engineer or equivalent.
• 5+ years of experience designing functional test equipment and PCBAs.
• Experience in Schematic Capture and PCBA layout.
• Working knowledge of scripting language to develop automation. Python, Matlab, PERL, Labview or SHELL.
• Understanding of peripherals and developing test and validation strategies.
• Experience with computer hardware communication bus protocols: USB, I2C, I2S, CSI, Ethernet, SPI, PCIe, HDMI, CAN, etc.
• Understanding of memory hierarchy and developing test and validation strategy.
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase.
• Collaborate with a cross-functional team to support product development from prototype to production.
• Currently possesses and is able to maintain an active U.S. Secret security clearance.

PREFERRED QUALIFICATIONS

• Master’s Degree in Electrical Engineering or equivalent.
• A detail-oriented individual who strives in an environment that values effective team collaboration.
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase.

Location

Palo Alto, CA

Job Description

Rhombus’ Data Engineers are instrumental in designing and implementing data engineering activities on topical, mission-driven projects that inform our national security agenda. They analyze, build, and maintain our organization’s data infrastructure and processing systems. 

Additionally, our Data Engineers perform various code development and query needs for integration with new and existing applications, dashboards and machine learning pipelines. Our Data Engineers work cross functionally with other departments to meet business needs. They utilize their skills at all stages of the analytics pipeline to create results that drive business values and customer success.

Responsibilities:

• Develop code using various programming and scripting languages to automate data ingestion and improve data management processes.
• Architect data repositories, stand up data platforms and develop data pipelines for ingestion, transformation, and aggregation.
• Review existing architecture, data strategy, and improve processes for data governance, data quality, and metadata management.
• Extract and analyze raw data from multiple data sources via APIs, SQL Stored Procedures, or Python scripts.
• Ability to develop scripts and programs for converting various types of data into usable formats and support project team to scale, monitor and operate data platforms.
• Collaborate with a multi-disciplinary team of analysts, data scientists, data engineers, developers, and data consumers in a fast-paced, agile environment.
• You’ll use your experience in analytical exploration and data examination while you manage the assessment, design, building, and maintenance of scalable platforms for clients.
• Communicate project status and results to various levels of leadership.

Qualifications:

• At minimum Bachelor’s degree in Data Analytics, Computer Science, Computer Engineering, Information Systems/Sciences, or other relevant area (or equivalent experience) and at least 3 years of professional experience, or a Master’s degree with strong academic project experience and one year of work experience.  
• Experience with 1 or more programming and scripting languages, with a strong focus on Python, Pandas and Numpy. Other languages include: Shell, PERL, Java, C/C++/C#, Scala, etc.
• Experience with 1 or more of the following relational, noSQL and/or file based storage (e.g. MYSQL, MongoDB, SQL Server, Oracle, Postgres, Hbase, DynamoDB, etc.)
• Experience building and maintaining ETL data pipelines
• Experience with software development life cycle including testing, documenting, delivery and support
• Working knowledge of AWS/cloud technologies
• Experience using query optimization as well as data modeling techniques.
• Familiarity with machine learning frameworks (such as TensorFlow, Scikit-Learn, etc.)

Personal Qualities:

• Bias for action: Rhombus seeks ‘doers’ who will get things done with accuracy, speed and at scale.
• Ability to contextualize data as it relates to Rhombus’ vision. We want someone who can understand the “why” and “so what”, and not just the “how”. Our Data Engineers help us transmit the enthusiasm we have around the data work to the individuals doing that work.
• Must have strong problem-solving skills and demonstrated excellent oral and written communication skills.
• We’re seeking folks with strong intellectual curiosity and creativity, with an ability and willingness to learn new skills and apply novel solutions to problems.
• Comfort in a fast-paced start-up environment is crucial, with the ability to consistently revise your approach in response to new information, and to be flexible and adaptive.

Salary Range

• The estimated base salary range for this position is $110,000 to $180,000/year

Benefits 

• Full medical, dental, vision coverage for employee and dependents 
• 401k matching program 
• PTO and Holidays 
• Bonus and other incentive programs
• Access to mental health program
• Access to Flexible Spending Accounts for Health Care, Dependent and Commuter

About Rhombus 

Rhombus Power Inc. (Rhombus) is a startup located in the heart of Silicon Valley at Stanford Research Park in Palo Alto.  We use cutting-edge cross-disciplinary approaches to solve pressing Big Data and Sensing problems in security, energy, and healthcare. Our advisory board includes two Nobel Laureates and a Draper Prize winner. 

Rhombus compensates, motivates, and develops employees, who are trusted, empowered, and involved. Employees have clear roles and expectations – and their roles are flexible enough to move at the speed of innovation in order to meet and exceed client expectations. We have a unique culture of global purpose, rooted in the innovation and progress of Silicon Valley. 

Rhombus knows that diversity is a condition for success. We are committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer. 

Join a team shaping the performance of next-gen CPUs and AI/ML chips. As a Physical Design Intern, you'll work hands-on from synthesis through tapeout, collaborating with top engineers to optimize some of the most advanced silicon in the world. 

This role is onsite, based out of Austin, TX or Santa Clara, CA.

Who You Are

• Currently pursuing a BS, MS, or PhD in EE, ECE, CE, or CS
• Solid understanding of logic design, VLSI, and transistor-level concepts
• Familiar with PnR tools, timing analysis, and power optimization techniques
• Comfortable scripting in Tcl, Perl, Shell, or Python

What We Need

• Support key physical design tasks—synthesis, floorplanning, PnR, clocking, timing closure
• Analyze and improve design PPA (Power, Performance, Area)
• Collaborate with front-end, PD, and architecture teams to influence early design decisions
• Explore and implement new flows, tools, or RTL experiments to optimize designs

What You Will Learn

• End-to-end physical design flow—from RTL handoff to final tapeout
• Deep dive into timing, power, EM/IR, and area trade-offs
• Industry-standard tools and techniques for modern chip development
• How top-tier silicon teams operate at scale

At Tenstorrent, we believe the future of computing must be open, which is why our interns don’t just watch from the sidelines – they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.

As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure the functional correctness and robustness of Tenstorrent’s next-generation RISC‑V and AI accelerator SoCs. You will work on building and improving modern verification environments, developing tests and checkers, and analyzing coverage to sign off complex digital IP and subsystems. Your work directly contributes to the reliability of the chips that power our AI and high‑performance computing roadmap.

We are looking for a minimum of 3 months for this role with the potential for extension to 6 months.

This role is hybrid, based in our Boston, MA office.

Who you are

• Pursuing a B.S. , M.S. or PhD. in Electrical Engineering, Computer Engineering, Computer Science, or a related field with a focus on digital design and verification.
• Strong understanding of digital logic design and computer architecture (pipelines, caches, interconnects, memory systems).
• Familiar with HDLs such as Verilog/SystemVerilog, and interested in learning Formal verification, Cocotb, and UVM‑based verification methodologies.
• Comfortable working in Linux-based development environments and using scripting languages (e.g., Python, Shell, Perl) to automate tasks.
• Detail-oriented problem solver who enjoys debugging complex issues, reasoning about corner cases, and working from specifications.
• Collaborative team member with clear communication skills, able to document work and discuss trade‑offs with RTL, architecture, and validation teams.

What We Need

• Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards.
• Write and refine verification test plans from architectural and micro‑architectural specifications, with a strong focus on corner cases and coverage.
• Develop constrained‑random and directed tests, run regressions, and triage failures by working closely with RTL designers to root-cause issues.
• Analyze functional and code coverage results, identify gaps, and propose additional tests or checks to drive coverage closure.
• Contribute to automation and infrastructure (scripts, Makefiles, CI hooks, dashboards) that improve verification productivity and debug turnaround time.
• Partner with cross‑functional teams (architecture, design, performance, validation) to align on expected behavior and sign‑off criteria for silicon.
• Have impact measured through coverage metrics achieved, quality and reproducibility of bugs found, and robustness of the verification environment you help build.

What You Will Learn

• End‑to‑end SoC design and verification flow for cutting‑edge RISC‑V and AI accelerator architectures.
• Industry‑standard verification methodologies (SystemVerilog/UVM), including testbench architecture, stimulus generation, and scoreboard/checker design.
• Hands-on experience with simulation, regression, and coverage tools used in large‑scale industrial verification environments.
• How to read and interpret hardware specifications, micro‑architecture documents, and timing diagrams, and translate them into actionable tests and assertions.
• Exposure to high‑performance interconnects, memory controllers, and accelerators, and how they are verified at IP, subsystem, and SoC levels.
• Best practices for collaborating in a silicon development team, including code review, documentation, and cross‑site communication.

USA Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Jan–Apr work term, Sept–Dec recruit.
• Summer Term: May–Aug work term, Oct–Apr recruit.
• Fall Term: Sept–Dec work term, Jan–Aug recruit.

Please note these timelines are for reference only. Actual timelines may vary.

Join the team building high-performance RISC-V CPU cores at Tenstorrent. As a Performance Verification Intern, you will work alongside CPU architects, micro-architects, and performance engineers to ensure our designs meet real-world performance demands. This is a hands-on role that spans simulation, emulation, debug, and analysis.

This role is on-site, full-time (40 hours/week) in Santa Clara, CA or Austin, TX.

Who You Are

• Pursuing a BS, MS, or PhD in EE, ECE, CE, or CS with strong academic performance.
• Experienced with assembly, C/C++, and scripting in Python or Perl.
• Familiar with CPU architecture and performance concepts, including pipelines, memory systems, and branch prediction.
• Comfortable working through complex debug problems in a methodical, detail-oriented way.
  
  

What We Need

• Interns who can create performance test plans and write stimulus to stress real CPU scenarios.
• Engineers who can run simulations and emulations to validate performance metrics.
• Contributors who can bring up and debug workloads ranging from open-source benchmarks to industry-standard suites.
• Teammates who can investigate mismatches between RTL and performance models and help root-cause bottlenecks.
  
  

What You Will Learn

• How CPU performance is measured, validated, and optimized before silicon.
• How performance models, RTL implementations, and debug tools come together in a real chip development workflow.
• Techniques for balancing tradeoffs in microarchitecture to hit performance targets.
• What it takes to collaborate across architecture, design, and post-silicon teams in a high-performance CPU project.

Tenstorrent is looking for a Staff Product Development Engineer - ATE Content Developer, who will be focused on core content development for high-performance AI/ML silicon. They  will be responsible for developing production test programs on ATE test platforms, translating DFT/ATPG content into optimized ATE solutions, and implementing Streaming Scan Network (SSN) architectures for efficient test data delivery. High level challenges include reducing test cost while maintaining coverage targets, optimizing test time for chiplet and multi-die architectures, and enabling rapid yield learning through robust test methodologies. The work is done collaboratively with a group of highly experienced engineers across DFT, design, product, and manufacturing domains.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced semiconductor test engineer with 7 years and a BS/MS in EE/ECE/CE and a track record testing complex digital devices on advanced nodes.
• Hands-on with Advantest V93K and/or Teradyne UltraFlex+ platforms, comfortable owning production test programs end‑to‑end.
• Deeply familiar with DFT/ATPG flows and test architectures: scan chains, MBIST, compression, JTAG/IEEE 1149.1, and common fault models (stuck‑at, transition, path delay, cell‑aware).
• Proficient in C/C++ or Java, with strong scripting skills in Python, Perl, or TCL to automate flows, pattern handling, and data analysis.
• Skilled at debugging across ATE hardware, test programs, and silicon, and at using data to drive root‑cause analysis and yield improvement.

What We Need

• Develop and optimize production test programs on Advantest V93K using the SmarTest 8 environment, from bring‑up through high‑volume manufacturing.
• Translate ATPG patterns (STIL/WGL) into production‑ready test content, balancing test time, coverage, and cost for chiplet and multi‑die AI/ML devices.
• Implement and debug Streaming Scan Network (SSN) based content for high‑speed scan delivery, ensuring robust and scalable scan test infrastructure.
• Own test content for scan, BIST, and memory test structures, collaborating with DFT teams on pattern debug, fault diagnosis, and coverage improvement.
• Support silicon bring‑up and debug in the lab and at manufacturing sites, including correlation, corner characterization, and PVT studies.
• Build and maintain automation scripts and test methods that improve productivity, repeatability, and quality across the test lifecycle.
• Document test architectures, flows, and debug procedures so they can be scaled across products, sites, and engineering teams.

What You Will Learn

• How to test and scale cutting‑edge AI/ML silicon with chiplet and multi‑die architectures, including exposure to 2.5D/3D packaging and HBM integration.
• Deeper expertise in SSN architectures, high‑speed scan delivery, and next‑generation DFT/test methodologies for complex HPC/AI devices.
• How to drive end‑to‑end yield learning: from ATE data and STDF analytics through to design, DFT, and manufacturing process feedback.
• How a fast‑growing AI hardware startup coordinates DFT, design, product, and manufacturing to bring new silicon from first silicon to high‑volume production.
• Opportunities to influence test strategy, infrastructure, and automation roadmaps for future products and platforms as Tenstorrent’s portfolio scales.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

Tenstorrent is seeking an experienced Silicon Validation Engineer to validate and qualify our cutting-edge die-to-die (D2D) subsystem, AI, and Processor IP testchips for the rapidly growing chiplet ecosystem. You'll develop hardware infrastructure for validation platforms, perform comprehensive electrical characterization, and support customer silicon bring-up. If you’re passionate about hands-on silicon testing and want to help usher in the chiplet era of semiconductor products, join us.

This role is on-site, based out of Santa Clara, CA; or Toronto, Canada. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with 5+ years of silicon test and characterization experience in lab environments.
• Expert with oscilloscopes, BERTs, and test equipment who can independently debug complex validation challenges.
• Self-driven problem solver with strong EE fundamentals in both digital and analog circuit design.
• Excellent communicator who collaborates effectively with design teams and tracks progress meticulously.

What We Need

• BS/MS in Electrical Engineering with 5+ years of hands-on silicon validation using Keysight/Tektronix equipment.
• Proven experience with high-speed measurements (Tx jitter, Rx JTOL) and test automation scripting (Python, Perl, LabVIEW).
• Strong understanding of datacomm circuits (amplifiers, PLLs, equalizers) and signal integrity concepts.
• Track record of independently running validation tests and driving issue resolution with design teams.

What You Will Learn

• State-of-the-art die-to-die chiplet validation methodologies for next-generation semiconductor architectures.
• How to build and evolve hardware infrastructure for advanced D2D validation and demo platforms.
• Customer-facing silicon bring-up techniques and product qualification best practices.
• The opportunity to shape validation standards in the emerging chiplet ecosystem at a fast-moving startup.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We’re looking for a Physical Design Engineer – EMIR to join our silicon team. In this role, you’ll lead EM and IR-drop simulations to ensure robust power delivery, signal integrity, and long-term reliability for high-performance ICs. You’ll work with RTL, physical design, and analysis teams to implement power grid strategies that optimize performance, power, and area (PPA), particularly at advanced nodes like 7nm and below. You’ll also support EMIR sign-off and waiver methodologies across the chip hierarchy.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A physical design specialist with deep experience in EMIR analysis and signoff.
• Comfortable navigating advanced technology nodes and power integrity challenges.
• Proactive and detail-oriented, with a passion for pushing performance and reliability boundaries.
• Collaborative and effective across teams working on RTL, physical design, packaging, and reliability.

What We Need

• 7+ years of experience in physical design or signoff, with a focus on EMIR.
• Hands-on with RedHawk, Voltus, or equivalent industry-standard EMIR tools.
  Strong understanding of IR-drop mitigation, EM compliance, and power grid design.
• Proficiency with layout extraction flows, RC modeling, and metal density checks.
• Experience working in advanced nodes (7nm, 5nm, 3nm), and with scripting languages like TCL, Python, Perl, or Shell.
• Knowledge of floorplanning, bump/RDL design, and sign-off flows (DRC/LVS, timing closure).

What You Will Learn

• How to architect and analyze robust power delivery for Tenstorrent’s RISC-V CPUs and AI chips.
• How to integrate EMIR signoff into fast-paced, high-performance chip design cycles.
• Best practices for hierarchical analysis and EMIR methodology across pre- and post-layout flows.
• Cross-functional collaboration for optimizing PPA while meeting stringent reliability goals.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX or Santa Clara, CA or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

What We Need

• BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs.
• Expertise with industry-standard tools (FusionCompiler, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python).
• Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling).
• Experience driving physical design requirements from early architecture through final signoff.

What You Will Learn

• How to implement cutting-edge AI accelerators, high-performance CPUs and the SOCs that host them on the most advanced process nodes.
• Innovative PPA optimization techniques and methodologies for next-generation chiplet architectures.
• End-to-end ownership from flow development to signoff in collaboration with architecture and IP teams.
• Direct impact on products that are redefining the landscape of AI and high-performance computing.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We’re looking for a Timing Engineer to join our silicon team. In this role, you’ll drive static timing analysis and closure for complex, high-performance designs. You’ll collaborate closely with logic, DFT, and physical design teams to debug constraints, optimize paths, and ensure our chips meet performance targets across corners and modes.

This role is hybrid, based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced in STA and passionate about enabling silicon to meet aggressive performance goals.
• Analytical and detail-oriented, with a strong understanding of timing paths, constraints, and optimization strategies.
• A collaborative team player who works well across logic, DFT, and physical design boundaries.
• Resourceful and self-driven, capable of developing scripts and methodologies that improve timing closure workflows.

What We Need

• 7+ years of industry experience and a proven record of successful tapeouts.
• Deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
• Proficiency in writing and debugging SDC constraints, creating ECOs, and developing closure strategies.
• Strong scripting skills in Python, Perl, and TCL to support automation and flow development.
• Familiarity with SPICE modeling and worst-case corner analysis.

What You Will Learn

• How to close timing on Tenstorrent’s high-performance RISC-V CPUs and AI SoCs.
• Advanced STA methodologies tailored to modern sub-micron process technologies.
• How to collaborate with world-class engineers across RTL, DFT, and physical design teams.
• How to influence chip performance through timing methodology innovation and automation.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a highly skilled and experienced Engineer to lead post-silicon power characterization and correlation activities for cutting-edge semiconductor products. In this role, you will be responsible for developing and executing detailed power measurement strategies on silicon, correlating results with pre-silicon models, and driving improvements across power architecture, design, and modeling methodologies. You will serve as a key technical leader, interfacing across design, architecture, validation, and systems teams to ensure silicon meets power and performance specifications under all operating conditions.

This role is hybrid, based out of Toronto, ON or Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• A Principal-level engineer with 8+ years in silicon power analysis and characterization, and a Master’s or PhD in EE, CE, or related field.
• Deep understanding of digital and mixed-signal power domains, including DVFS, leakage vs. dynamic power, and power gating.
• Highly proficient in lab-based power measurement using oscilloscopes, current probes, power analyzers, and SMUs, plus Python/Perl/MATLAB for automation and analytics.
• A strong debugger and collaborator, comfortable driving cross-functional investigations and clearly communicating technical findings.

What we need

• Own the post-silicon power measurement strategy end-to-end across operating modes, voltages, frequencies, and workloads.
• Build and maintain lab infrastructure, automated workflows, and data analysis pipelines for high-fidelity, repeatable power characterization.
• Correlate silicon power data to pre-silicon models (RTL, gate-level, sign-off), drive root-cause analysis, and refine power estimation methodologies with design and modeling teams.
• Characterize power across PVT corners and work with bring-up/validation teams to develop test content, debug power anomalies, and ensure products meet power and performance specs.

What you will learn

• How state-of-the-art SoCs behave in real silicon across diverse workloads, system configurations, and operating conditions.
• How to influence power architecture, RTL design, and modeling flows by feeding silicon insights directly back into early design phases.
• Best practices for building scalable, automated post-silicon power infrastructures that support multiple products and generations.
• Advanced correlation, margining, and variability analysis techniques that deepen your expertise in both SoC-level power and system-level behavior.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Hudson River Trading (HRT) is looking for an Electronic Trading Support Engineer to join our global Trade Operations (TradeOps) team in NYC. This team is responsible for managing HRT’s live trading environment, one of the most robust and efficient electronic trading platforms in the world. This includes configuring, monitoring, and optimizing the firm’s trading as well as handling risk, regulatory, and development tasks. The TradeOps team focuses on both automating common tasks and preparing for the unexpected. Your day could consist of debugging to get a process running in time for the market open, making a difficult on-the-spot decision that balances compliance, risk, and PnL during trading hours, or coordinating the technical rollout of a new trading strategy. 

Being a member of TradeOps at HRT means working on a tight-knit, highly productive team. We're looking for someone who loves technology and wants to work on a broad range of projects using whatever tool(s) best solve the problem at hand. Excellent communication is a must, along with a can-do attitude.

Role

In a high performance environment, immediate awareness of and reaction to systems and trading issues is essential. That’s where HRT’s Electronic Trading Support Engineers come in. You’ll be responsible for managing new initiatives and ensuring a smooth trading day. You’ll act as the first line of defense when the inevitable happens, and the subject matter expert on recent changes to the production trading platform. The team’s scope covers everything from systems infrastructure, to compliance, risk management, overnight clearing, and performance improvement. 

Responsibilities 

• Support live trading during US market hours
• Handle order flow from HRT’s trading desks
• Respond to external market alerts and outages
• Interface with exchanges & other external parties to support trading 

Qualifications

• Bachelor’s degree in a quantitative discipline (CS, Engineering, Physics, Math, etc.)
• Working knowledge of UNIX systems
• Experience with a scripting language (Python, Perl, Bash)
• Excellent communication skills and enjoy interfacing with clients, both internal and external
• Incredibly organized, with a high attention to detail
• Excited to work independently in a very fast-paced, high pressure environment
• Poses an understanding of Market Data/Order Entry systems and an interest in how modern electronic markets work
• Industry experience and/or Series 7 or 57 certification is preferred

The estimated base salary range for this position is 100,000 to 150,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is looking for a Junior Electronic Trading Support Engineer to join our global Trade Operations (TradeOps) team in NYC. This team is responsible for managing HRT’s live trading environment, one of the most robust and efficient electronic trading platforms in the world. This includes configuring, monitoring, and optimizing the firm’s trading as well as handling risk, regulatory, and development tasks. The TradeOps team focuses on both automating common tasks and preparing for the unexpected. Your day could consist of debugging to get a process running in time for the market open, making a difficult on-the-spot decision that balances compliance, risk, and PnL during trading hours, or coordinating the technical rollout of a new trading strategy. 

Being a member of TradeOps at HRT means working on a tight-knit, highly productive team. We're looking for someone who loves technology and wants to work on a broad range of projects using whatever tool(s) best solve the problem at hand. Excellent communication is a must, along with a can-do attitude.

Role

In a high performance environment, immediate awareness of and reaction to systems and trading issues is essential. That’s where HRT’s Electronic Trading Support Engineers come in. You’ll be responsible for managing new initiatives and ensuring a smooth trading day. You’ll act as the first line of defense when the inevitable happens, and the subject matter expert on recent changes to the production trading platform. The team’s scope covers everything from systems infrastructure, to compliance, risk management, overnight clearing, and performance improvement. 

Responsibilities 

• Support live trading during US market hours
• Handle order flow from HRT’s trading desks
• Respond to external market alerts and outages
• Interface with exchanges & other external parties to support trading 

Qualifications

• Bachelor’s degree in a quantitative discipline (CS, Engineering, Physics, Math, etc.)
• Working knowledge of UNIX systems
• Experience with a scripting language (Python, Perl, Bash)
• Excellent communication skills and enjoy interfacing with clients, both internal and external
• Incredibly organized, with a high attention to detail
• Excited to work independently in a very fast-paced, high pressure environment
• Poses an understanding of Market Data/Order Entry systems and/or an interest in how modern electronic markets work
• Industry experience and/or Series 7 or 57 certification is preferred if applicable, but not required - recent graduates with relevant knowledge can be considered

The estimated base salary range for this position is 100,000 to 150,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

At Visual Concepts, we believe great games are made by diverse and empowered teams with a shared passion for play. As one of the world’s top game development studios, we have shipped over 100 multi-sku titles to critical acclaim and commercial success. Our teams are independent and ambitious. Our studios in Novato, Irvine, Budapest, Shanghai, Austin, Boise, Seoul and Parksville, Canada are committed to artistry and ground breaking technology, offering top candidates the opportunity to learn and grow with some of the hardest working and most creative minds in the industry.

What We Need:

We’re seeking a Senior Engineer with a passion for server-side development to join the NBA 2K team! In this role, you’ll take ownership across a broad technical landscape- working in distributed systems, large-scale computing, and efficient databases to build high-performance backend services. Your work will play a key role in delivering world-class online experiences that power one of the most popular sports game franchises in the world. This role reports into Lead Director of Programming.

What You Will Do:

• Work in the backend architecture and services that support NBA 2K’s online features
• Design and optimize distributed systems to ensure scalability, reliability, and fault tolerance
• Build and maintain large-scale computing solutions that handle millions of concurrent players
• Develop efficient database structures and queries to support high-volume, real-time transactions
• Deliver high-performance backend services with a focus on low latency and stability
• Partner with engineering and design teams to enable seamless online gameplay experiences.

Who Will Be A Great Fit:

• 5+ years of professional software development experience, with a strong focus on backend and server-side systems
• Strong proficiency in C++ with a solid understanding of object-oriented programming principles
• Proficiency in one or more scripting languages such as Python, PHP, Perl, or Ruby, with a strong preference for Python
• Understanding of distributed and scalable systems
• Proven experience with multithreaded programming, driving efficiency and stability across large-scale, real-time environments
• Demonstrated ability to research, evaluate, and integrate emerging technologies and trends to enhance team capabilities, platform performance, and product innovation
• BS in Computer Science or equivalent experience in large-scale software development
• Experience developing secure transaction systems, including virtual currency and account-based features, a strong plus
• Skilled in database optimization, including connection management and query performance tuning
• Familiarity with online gaming architectures and service design for live, connected player experiences
• Working knowledge of SQL databases such as MySQL, Microsoft SQL Server, or similar systems
• Video game console development experience is highly beneficial
• Love for video games (not just ours!)

This is a fully remote role that may be based anywhere in the United States. Below are the expected salary and wage ranges for applicants based in locations where the pay transparency law is in effect: California: $130,700 - $174,300 per year. New York State (inclusive of New York City): $117,700 - $157,000 per year. Washington: $130,700 - $174,300 per year. New Jersey: $117,700 - $157,000 per year. British Columbia: $115,700 -$154,300 (CAD) per year. However, base pay offered is based on market location, and may vary further depending on individualized factors for job candidates, such as job-related knowledge, skills, experience, and other objective business considerations. Subject to those same considerations, the total compensation package for this position may also include other elements, including a bonus and/or equity awards and eligibility to participate in our 401(K) plan and Employee Stock Purchase Program. Regular, full-time employees are also eligible for a range of benefits at the Company, including: medical, dental, vision, and basic life insurance coverage; 14 paid holidays per calendar year; paid vacation time per calendar year (ranging from 15 to 25 days) or eligibility to participate in the Company’s discretionary time off program; up to 10 paid sick days per calendar year; paid parental and compassionate leave; wellbeing programs for mental health and other wellness support; family planning support through Maven; commuter benefits; and reimbursements for fitness-related expenses. Ontario only: The use of Artificial Intelligence is not being used to screen candidates. The position is for an existing vacancy.

To learn more about Visual Concepts and our studio locations, check out our website at www.vcentertainment.com

As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person.

Key Responsibilities

• Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.
• Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.
• Define and manage I/O timing budgets across hierarchical designs.
• Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.
• Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.
• Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.
• Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
• Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
• Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.

Basic Qualifications

• Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
• ≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
• Experience working with IP vendors for both RTL and hard-macro integration.
• SystemVerilog/Verilog familiarity.

The base salary range is USD 209,000.00 USD – USD 250,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.

Basic qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred.
• ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications.
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
• Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.
• Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.
• Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.
• Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.

Preferred Experience

• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Experience with directed test based methodologies, cache verification and formal methods.

The base salary range is USD 160,000.00 – USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.

Key Responsibilities

• As Physical Design CAD Engineer you will support and build flows for world class EDA tools.
• Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems.
• Architect and recommend flow improvements and enhance existing methodology for high performance design.
• Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc.
• Work with cross function teams to define requirements and specifications to achieve best PPA
• Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity
• Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.

Basic Qualifications

• Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
• 2-10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

• Knowledge of agentic AI solutions is a plus.
• Experience working with EDA/IP vendors for both RTL and hard-macro integration.
• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.

About Epirus  

Epirus is a high-growth technology company dedicated to overcoming the asymmetric challenges inherent to the future of national security. Epirus' flagship product, Leonidas, is a software-defined system built using intelligent power management techniques which allow power-hungry systems to do more with less.

Job objective: This is an exciting role an innovative, high-growth defense technology company. The ideal candidate for the position is someone who has experience designing, verifying, and integrating state-of-the-art FPGA systems and embedded processing solutions for RF applications. As a Sr. FPGA Engineer, you will work closely with a talented, multi-disciplinary engineering team in a fast-paced environment to apply emerging technologies in innovative ways to rapidly produce new products.     

Duties  

• Design and verification of RTL modules for FPGA applications
• Ownership of entire FPGA designs from initial architecture trades through implementation, verification, and hardware bringup, including FPGA sizing estimation and IO planning.
• Lead initial testing and bring-up of custom FPGA circuit cards, validating functionality of on-board peripherals including memory interfaces, Ethernet controllers, and integrated sensors.
• Automating test environment (up to and including hardware-in-the-loop testing), lab equipment, and measurement devices
• Capturing design tradeoffs, state machine flow, system address maps, and block diagrams 

Required Qualifications  

• Bachelor’s degree in Electrical Engineering or a related field.
• 5+ years of experience in FPGA design, implementation, and testing
• Extensive experience implementing FPGA designs and embedded processing designs on embedded hardware
• Experience working with latest generation state-of-the-art Xilinx/Intel Parts and associated tool sets (Vivado, Quartus)
• Understanding of common digital communication protocols (SPI, I2C, UART)
• Development Experience of Integrated Embedded Applications (ARM, GPU)
• Experience with standard bus and streaming protocols, such as AXI and AXI-Stream
• Experience with Continuous Integration and Continuous Delivery processes
• Active Secret or Top Secret clearance, or ability to obtain one desired but not required.  

Desired Qualifications   

• Experience with design automation, scripting languages (TCL, Python, Perl, Matlab)
• Knowledge of Advanced Firmware Verification Testbench Development (UVM, System Verilog)
• Skilled with Advanced High-Speed Verilog/VHDL Designs including High Speed Memory Interfaces (DDR4, HBM) and High Speed SerDes IO and Protocols (100GE, JESD204B, Interlaken)
• Experience implementing Complex DSP Algorithms on FPGAs using tools such as Matlab, Simulink, HDL Coder to implement advanced communications or other designs in FPGA
• Experience collaborating with software engineering team in an SoC environment to develop designs that incorporate HDL combined with embedded Linux
• Good written and oral communication skills
• Collaborative; capable of working across all levels of the organization
• Organized; comfortable working in a fast-paced, ever-changing environment 

The Opportunity:

As an Executive Director and Head of Research Computational Biology within our Biology Function, the individual will oversee the scientific and strategic direction of systems biology research and preclinical computational biology initiatives. The individual will lead a team of computational biologists and bioinformaticians focused on acquisition, organization, and analysis of large multi-omics data sets, using both public and proprietary data sources, that will help inform treatment strategies and guide patient stratification for a growing pipeline of RAS(ON) and targeted oncology therapeutics. We are looking for an experienced leader with strong interpersonal skills and an ability to lead a strong and diverse computational biology team. Key aspects of the role include:

• Strategic vision and leadership: Develop and implement a long-term strategy for research systems biology and bioinformatic activities to support a growing pipeline of RAS(ON) and novel targeted inhibitors. Lead and supervise a team of experienced computational biologists and bioinformaticians to generate, organize, and interpret large data sets to inform therapeutic and combination strategies for patients with cancer.

• Cross-functional collaboration across research, translational, development and medical affairs groups: Work across functions to support advancement of programs from early discovery into clinical development using biological insights derived from computational approaches. Additionally, leverage clinical data from RVMD investigational agents to generate proprietary insights into RAS mutant tumor biology and RVMD RAS(ON) inhibitor mechanisms of action.

• Technical leadership and innovation: Lead a team analyzing large, high-dimensional datasets. Work with colleagues in Information Sciences and Information Systems to oversee data integration, analysis and visualization using cloud-based platforms (AWS, Azure, GCP). Direct the development and application of cutting-edge statistical analysis, AI/ML methods, generative AI models, and MLOps principles to elucidate findings and generate new insights related to biomarker discovery, drug target identification, and predictive modeling. Establish and implement modern workflow management systems (Snakemake, Nextflow) and reproducible research practices.

• External collaboration: Cultivate and manage academic and industry collaborations, including CRO partnerships. Represent the company at scientific conferences through presentations and thought leadership. Maintain an active publication record in high-impact, peer reviewed journals. Drive intellectual property strategy and patent filings related to computational discoveries.

Required Skills, Experience and Education:

• Education: A Ph.D. in systems biology, computational biology, bioinformatics, or a related biological or biomedical discipline.

• Experience: Minimum of 15+ years total experience with significant pharmaceutical/biotechnology industry and management experience.

• Scientific knowledge: Deep expertise in systems biology, computational biology, and bioinformatics, including proficiency with multi-omics data integration, modeling, and analysis. Experience with single-cell technologies, spatial transcriptomics, proteomics, and epigenomics. Oncology research experience preferred but not required.

• Technical: Advanced programming skills in R, Python, and at least one additional language (Perl, C/C++, Java). Proficiency with high-performance computing (HPC) and cloud platforms (AWS, Azure, or GCP). Knowledge of workflow management tools and version control systems. Understanding of MLOps principles, model deployment, and generative AI applications in drug discovery.

• Leadership and management: Demonstrated ability to lead, mentor, and inspire interdisciplinary teams while fostering a collaborative culture. Experience managing budgets and strategic planning at the department level. Proven track record of advancing research programs from discovery through development.

• Strategic thinking: Proven strategic thinker who can align research and drug development objectives and leverage innovative technologies effectively.

• Communication: Excellent communication and presentation skills for interacting with technical teams, senior leadership, and external partners. #LI-Hybrid  #LI-GL1

The Challenge

We are hiring a DevOps Engineer who will collaborate between our Engineering and Cloud Ops teams. DevOps Engineers build out the automated infrastructure and tooling for development, testing and production environments. DevOps Engineers contribute to productizing new software by developing installation, deployment and maintenance scripts.

Your Mission

• Develop and maintain an understanding of the software development and deployment pipeline - This includes initial software architecture and development, the continuous integration workflow, deployment of software through production.  
• Design, build and maintain automation that powers our cloud-based product deployments and auto-scaling with zero downtime and the ability to easily rollback.  
• Support application infrastructure to ensure the OneTrust platform is optimized for performance and reliability  
• Build and maintain supporting infrastructure for cloud environments through an “infrastructure as code” methodology  
• Perform and automate system administration services including installation, configuration, maintenance, and disaster recovery  
• Identify emergent issues that indicate scalability and reliability problems, working with development and operations teams to help drive solutions  
• Identify system level issues related to OS configuration and virtual hardware bottlenecks  
• Manage incident response protocol and provide hands-on direction during service interruptions - Assist with Root Cause Analysis of service interruptions and maintain SLA  
• Automation, auditing, and other tooling for security, compliance, and resource usage - Monitor and improve processes for all deployments  
• Mentor other engineers to deliver quality standards  

You Are

• Highly organized and meticulous with excellent process management skills 
• Self-motivated and technically curious, able to leverage self-directed time and able to prioritize and manage multiple tasks  
• Able to function in a rapidly changing environment  
• Someone with good verbal and written interpersonal skills – you are able to clearly and effectively articulate ideas and direction of projects  
• Passionate for high quality work and attention to detail 

Your Experience Includes

• Bachelor's degree in Computer Science, Engineering, or related technical or business field  
• 4+ years as Software Developer, Systems Engineer, or DevOps Engineer  
• Experience with infrastructure automation using Docker, Chef, Terraform, or equivalent  
• Strong distributed systems knowledge and web services design, implementation, and/or operation experience  
• Hands on experience with CI/CD pipeline and tools (Jenkins or similar tools)  
• A working understanding of code and script (Java, Python, Perl, and/or Ruby) 
• Agile development (Scrum, XP, or Kanban) experience 
• Ability to use a wide variety of open source technologies and cloud services (Azure, Google, or AWS) 
• Knowledge in collecting distributed logs/events and automating triggers based on events (Elastic Stack or similar)

Extra Awesome

• Experience in setting up and scaling message brokers like Kafka or equivalent
• Experience in setting up and scaling NoSQL document databases like MongoDB or equivalent
• Experience with Kubernetes management platform like AKS, EKS, GKE or equivalent