Position Description:

The Services PreSales Architect is a technical authority on both cloud and on-premises based IAM systems and is responsible for ensuring the successful design and implementation of Okta’s & Auth0’s industry leading cloud identity platform for our customers. Your main focus will be on driving the success of Okta's and Auth0's identity offerings. You will cultivate strong, trusted partnerships with customers, concentrating on their success and helping them achieve their business goals by promoting innovative and creative solutions. A key part of your role is to translate customer business needs and insights into a clear, actionable strategy that the delivery team can execute to help customers achieve tangible results and high business value from their initiatives. This is a key member of the Professional Services (PS) Pre-Sales team.

Job Duties and Responsibilities:

• Lead the pre-sales discovery of functional and technical requirements required to establish an Identity platform for our customers. 
• Lead Partners, Customers and Engagement Managers to document and mitigate technical risk identified during discovery.
• Create estimates to implement the proposed solution.
• Review services estimates to ensure project scope can be successfully delivered as outlined - technical risk is appropriately mitigated and timelines follow staffing guidelines.
• Lead and develop co-delivery proposals by identifying and engaging appropriate partners.
• Drive New Product Introduction (NPI) across PS by training Engagement Managers and developing associated assets such as scope modules, SKUs, success stories and enablement toolkits.

Minimum REQUIRED Knowledge, Skills, and Abilities:

• 10+ years of overall IT / software development experience, solution design and technical architecture experience
• 5+ years of Okta implementation experience
• 5+ years of consulting experience
• 5+ years driving application architecture design
• 5+ years of experience with (IAM) architectures
• Experience with employee and customer identity use cases: HR driven identity, Active Directory, SSO, SaaS application integrations.
• Experience with Identity Governance and Privileged Access Management use cases. 
• Demonstrated ability to work and interact with high-level customer executives and technical resources.
• Experience in leading discovery workshops to derive customer requirements and specifications.
• Experience in developing functional specifications and system design specifications for customer engagements.
• Strong knowledge of Security Architecture, Design and Operations, LDAP, Active Directory, SSO, SAML, OIDC, RBAC, OAuth, JSON, REST.
• Experience integrating with a multitude of On-Prem and SaaS based products.
• Exhibits confidence and a deep understanding of emerging industry practices when solving business problems.
• Identifies critical issues with ease.
• Effectively communicates technical information to non-technical audiences.
• Manages customer expectations effectively.
• Application design experience.
• Clear and Dynamic Communication.
• Ability to travel up to 50%

Highly Desirable Knowledge, Skills, and Abilities:

• Knowledge of software development security and cryptography.
• Familiarity with IAM solution providers.
• Experience with API Gateways, CASB, and Reverse Proxies (NGINX)
• Proficiency with various open-source software and development tools
• Proficiency in one or more of the following: .Net, Ruby, Java, Python or Perl

Education and Certification

• A Bachelor’s degree (or equivalent) in Computer Science, Information Technology or related discipline required.
• Okta Certified Technical Architect or a combination of Okta Certified Consultant and Okta Certified Developer is a plus.
• CISSP certification is a plus.
• TOGAF certification is a plus.

#LI-BF1

#LI-Hybrid

P10902_3357735

The Role 

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews and microarchitecture discussions. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
• Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
• Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
• Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git). 

Nice to Have

• Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management.
• Familiarity with developing and integrating reference models.
• Understanding of RTL design flows and some industry standard interfaces (ex: APB/AHB/AXI).
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

• Base salary range for this role is $130,000 – $200,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
• Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
• Participate in ASIC team interviews.
• Drive advancement of DV methodologies and improvements.
• Manage external IP providers and verification partners when needed.
• Take lead on large and/or complex systems. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
• Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
• Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
• Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
• Experience with developing and integrating reference models.
• Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
• Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
• Involvement in post-silicon validation planning and execution. 

Nice to Have

• Experience with low power verification.
• Experience with analog behavioral models.
• Familiarity with physical design flows.
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

• Base salary range for this role is $190,000 – $285,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
• Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
• Participate in ASIC team interviews.
• Contribute to advancement of DV methodologies and improvements.
• Engage external IP providers and verification partners when needed. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
• Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).
• Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
• Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
• Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).
• Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++). 

Nice to Have

• Experience with developing and integrating reference models.
• Understanding of low power verification.
• Familiarity with gate-level simulation and analog behavioral models.
• Involvement in post-silicon validation planning and execution.
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 
  

Compensation and Benefits:

• Base salary range for this role is $170,000 – $250,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

We are looking for a Senior Technical Designer to own Narrative Scripting – specifically level dialogue implementation in our upcoming AAA third-person action-adventure game. As a key member of the design team, you will drive interactive story and dialogue in the play space. The ideal candidate has experience working with narrative, design, audio, and other stakeholders to ideate, plan, and implement scripted dialogue on shipped AAA titles.

Responsibilities:    

• Work with engineering, animation, and design teams to implement content, solve workflow issues, and create content pipelines.  
• Collaborate closely with writers, game designers, and audio designers to develop a comprehensive plan for level dialogue that supports the game’s creative direction and narrative goals. 
• Create supporting documentation that helps facilitate clear, efficient writing for the other members of the narrative team.  
• Research and collaborate with subject matter experts to ensure all grounded, real-world aspects of the story, characters, and world are represented with empathy and authenticity. 
• Support other aspects of narrative and game design in general, including implementing environmental storytelling or other tasks within the design department. You may also be asked to attend voiceover recording sessions and write, review, and/or edit text and dialogue. 

Requirements & Skills:   

• Proficiency in using Unreal 5, particularly in implementing narrative elements and working with Blueprint. 
• Knowledge of and interest in the type of game we are making.  
• Interest in establishing story intent and pacing for mission dialogue. 
• Substantial experience with scripting, branching dialogue, and other technical aspects of narrative design in game development. 
• Experience with text-based scripting and programming languages (e.g. XML, PERL, C++) is a bonus. 

Qualities: 

• We believe in ownership, so the more of your vision that you can prototype with your own skills, the better.  
  The ability to take and deliver feedback and constructive criticism. 
• Self-directed and comfortable working and delivering in a dynamic and fast-paced creative environment. 
• High attention to detail and commitment to quality. 
• Excellent communication and teamwork skills, with the ability to work collaboratively across disciplines. 
• A passion for storytelling and a creative mindset that can bring new ideas and fresh perspectives to the project. 
• A generalist. Learn whatever skills will help you complete your vision. From making prototype assets, to animation, VFX, mocap, audio, etc – a designer is a versatile person. You will have stellar artists and engineers to help you, but the more you can present a singular vision to us with your prototype work, the more excited we will get about it!   
• Responsible. You will be checking in script and level content without review. It’s your job not to break the build. 

(This is a temporary “Project Hire” position. The anticipated duration of this assignment will vary. TNM Project Hire employees will be eligible to participate in a number of TNM benefit plans such as medical, dental, vision, 401(k) matching, and flexible PTO)

TNM considers a number of factors when determining each role's base pay range, including industry benchmarks, location, experience, and other job specific skills. In addition to base pay, this role may be eligible for other incentive compensation including equity and profit share. The estimated base pay range for this role is U.S. only and not applicable for locations outside of the U.S.

The estimated base pay range for this role is:  $120k - $145k

THE OPPORTUNITY

Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment.  FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D.  These are exciting projects aimed at addressing challenging real-world communication needs. 

This Principal FPGA / RTL Design Engineer position is based at Silvus headquarters in the heart of vibrant West Los Angeles, CA and is on a hybrid schedule.  A minimum of 3 days onsite per week is expected. On-site days are Mondays, Wednesdays, and Thursdays.

The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion.

ROLE AND RESPONSIBILITIES

• Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks.
• RTL coding, simulation, and test bench development.
• FPGA synthesis and timing closure.
• Hardware verification and troubleshooting; familiarity with logic analyzers.
• Provide support to the RF and Software Engineering Teams.

REQUIRED QUALIFICATIONS

• Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields.
• Minimum 10 years of demonstrated experience in RTL design and FPGA implementation; 8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields.
• Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs.
• Deep knowledge of RTL design fundamentals using Verilog and System-Verilog.
• Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
• Must be U.S. Person (U.S. Citizen, or Permanent Resident) due to clients under U.S. federal contracts
• All employment is contingent upon the successful clearance of a background check.

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES

• MS. or Ph.D. degree in Electrical Engineering, Computer Science, or relevant fields.
• Basic MATLAB skills.
• Solid knowledge and understanding of scripting languages such as Perl and Python.
• Strong communication and presentation skills.
• Experience with wireless communication systems on FPGA or ASIC designs.

WORKING CONDITIONS & PHYSICAL REQUIREMENTS

• Office environment.
• Occasional exposure to heat, cold, and allergens while performing tests or demonstrations in the field.
• While performing the duties of this job, the employee is required to do the following:
  • Lift equipment up to 20 lbs. for the set-up of demonstrations and testing.
  • Perform bending and reaching movements to place items on lower and higher shelves.
  • Kneeling or squatting to access lower shelves.
  • Walking/Moving in the labs