We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance-aware design.

This role is hybrid, based out of Toronto, Ottawa, Boston, or Austin. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A digital design expert with a deep understanding of computer architecture and IP microarchitecture.
• Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows.
• Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals.
• A naturally collaborative and technical engineer — you thrive in spec definition, peer reviews, and team-wide planning.

What We Need

• Architecture and RTL implementation of Tenstorrent’s custom IP blocks and SoC components.
• Performance-aware design decisions for compute, interconnect, or memory-heavy blocks.
• Occasional contributions to validation using emulation, FPGA prototyping, or UVM flows.
• Strong synthesis and timing closure awareness to support backend teams.
• Prior experience in on-chip fabric and interconnect designs is an asset.

What You Will Learn

• How cutting-edge AI chips are built, from spec to silicon.
• What it takes to collaborate with teams designing novel processor and memory architectures.
• How to blend custom logic with standard SoC elements for power and scale.
• How cross-functional workflows come together across design, DV, physical, and firmware teams.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Proto is accelerating the world's transition to an open economy with products that increase access and independence for everyone. We're building Bitkey, a simple and safe self-custody bitcoin wallet that will put customers in control, as well as hardware and software that will help decentralize bitcoin mining and enable new and innovative use cases for bitcoin mining. We're developing these products in the open - you can read more about them at bitkey.build and mining.build. Within Proto, our Bitcoin Products team delivers the product and go-to-market strategy, software, firmware, and custom silicon needed to make Bitkey and our ambitious mining initiatives a reality. Come build the future of money with us!

The Role

We are looking for an ASIC Validation Engineer to help bridge the gap between custom mining silicon design and real-world operation. In this highly hands-on, lab-focused role, you'll work closely with ASIC designers and system engineers to debug issues, build test infrastructure, and generate the data needed to enable rapid design iteration and system-level development.

You Will:

• Bring up new silicon on bench platforms, evaluation boards, and system hardware
• Debug issues across ASIC, board, firmware, and system interactions
• Develop bench tests, scripts, and tools to exercise silicon features and collect data
• Build and maintain test setups (lab automation, instrumentation, fixtures, scripts)
• Partner with ASIC designers to validate functionality and root-cause failures
• Work with system engineers to ensure silicon performs correctly in target system environments, including mining systems
• Generate and analyze data to support design decisions, characterization, and bring-up
• Create lightweight, reusable test workflows and documentation for the broader team
• Support early manufacturing efforts with practical validation and debug, as needed
• Travel up to 20% to the labs in Oakland, CA or Toronto, Canada

You Have:

• Bachelor's degree in Electrical Engineering or related field
• 4+ years of experience in silicon validation, hardware test, or related roles
• Strong hands-on experience in a lab environment (bench bring-up, debugging, instrumentation)
• Solid understanding of digital systems and basic analog concepts
• Experience writing scripts or tools (Python preferred) for test and data analysis
• Comfortable debugging issues that span multiple layers (ASIC ↔ board ↔ system)
• Clear communication skills and ability to work closely with cross-functional teams

Preferred:

• Experience with ASIC or FPGA bring-up and validation
• Familiarity with common interfaces (SPI, I2C, JTAG, UART, etc.)
• Experience using lab equipment (oscilloscopes, logic analyzers, power supplies, etc.)
• Exposure to high-performance, power-dense systems (e.g., mining ASICs, accelerators, or similar)
• Experience building test automation or internal tooling
• Familiarity with data analysis and visualization

Nice to Have

• Experience working with early silicon / first bring-up environments
• Exposure to manufacturing test or ATE
• Experience working on systems with tight power, thermal, and performance constraints