Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off, including opportunities for full-chip ownership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

We are seeking a Hardware Electronics Design Engineer to design, develop, and validate high-speed and high-power electronic systems. This role involves schematic design, PCB development, signal and power integrity, and hands-on bring-up of complex hardware. The engineer will work closely with system, mechanical, firmware, and manufacturing teams to deliver reliable, high-performance products from concept through production.

The ideal candidate has deep experience with high-speed interfaces and power delivery, and is comfortable owning designs through debugging, validation, and manufacturing release.

Key Responsibilities

• Design and develop high-speed (PCIe/Ethernet) electronic circuits and systems
• Design power delivery networks (PDN) including DC-DC converters, multi-phase VRMs, and protection circuits
• Create schematics, BOMs, and design documentation for complex PCBs
• Lead board-level architecture decisions including power topology, interface selection, and component choice
• Work with PCB layout engineers to ensure proper stack-ups, routing, and return paths
• Address thermal considerations in collaboration with mechanical and thermal teams
• Lead board bring-up, debug, and root-cause analysis of hardware issues
• Use lab equipment (oscilloscopes, network analysers, power analysers) to validate performance
• Support compliance, reliability, and environmental testing
• Support DFM/DFT reviews and transition designs into manufacturing

Qualifications & Experience

• Diploma, Bachelor’s or Master’s degree in Electrical or Electronic Engineering, or equivalent experience
• 7+ years of experience in hardware electronics design
• Proven experience designing high-speed digital and high-power circuits
• Experience taking designs from concept through production

Technical Skills

• High-speed digital design (DDR, PCIe, Ethernet, SerDes)
• Power electronics and PDN design (buck/boost converters, VRMs, protection)
• Signal integrity (SI) and power integrity (PI) principles
• Schematic capture and PCB tools (Xpedition, Altium, Cadence, or equivalent)
• Hardware debug and lab instrumentation

Preferred Experience (Nice to Have)

• Experience with multi-layer high-speed PCBs (10+ layers)
• Familiarity with SI/PI simulation tools
• Experience with compliance testing (EMI/EMC, safety)
• Experience with AI accelerator or HPC hardware
• Thermal Management: Knowledge of techniques to manage heat dissipation in high-power systems

   How we work

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is

About us

• Founded in 2022, team of 70+ which is expanding rapidly
• Modern, open offices in London and Bristol
• Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency

Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

We are looking for a highly motivated and experienced RTL Design Engineer to join our dynamic team. In this role, you will play a key part in the design and implementation of digital systems, contributing to every stage of the project lifecycle. Your work will involve developing and optimising Register Transfer Level (RTL) designs for high-performance and power-efficient systems

RTL Development and Implementation:

• Develop and maintain RTL specifications for digital designs, ensuring clarity and accuracy.
• Implement complex design modules with a focus on performance, power, and area efficiency.
• Take ownership of design tasks, including planning, execution, and delivery of work packages.
• Define design tasks for the project, including partitioning, interface specifications, and module definitions.
• Collaborate with verification engineers to ensure functional correctness through simulation and formal verification.

Cross-Functional Collaboration:

• Work closely with physical design engineers, and verification teams to ensure seamless integration of the design.

Documentation and Standards Compliance:

• Document RTL design methodologies, module interfaces, and functional requirements.
• Ensure adherence to coding standards, best practices, and maintainability guidelines.

Qualifications and Skills:

Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.

Experience:

• 6+ years of experience in digital design, RTL development, or related roles.
• Proven expertise in developing RTL designs for high-performance systems.
• Familiarity with advanced digital design concepts, such as pipelining, clock-domain crossing, and power gating.
• Experience with high-speed or low-power design methodologies.

Soft Skills:

• Strong analytical and problem-solving skills.
• Effective communication and collaboration abilities in cross-functional teams.
• A detail-oriented approach with a focus on quality and efficiency.

How we work

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is

About us

• Founded in 2022, team of 70+ which is expanding rapidly
• Modern, open offices in London and Bristol
• Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency

Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

We are seeking an experienced PCB Layout Engineer to deliver complex, high-speed and high-power PCB designs while also owning PCB library creation, validation, and ongoing management. This role plays a critical part in ensuring electrical performance, manufacturability, and long-term design quality across multiple products. The ideal candidate combines deep layout expertise with a strong understanding of component footprints, land patterns, and library governance best practices.

Key Responsibilities

PCB Layout & Design Execution

• Create PCB layouts for complex, multi-layer boards supporting high-speed digital and high-power circuits
• Own component placement, routing, and constraint implementation from concept through manufacturing release
• Collaborate closely with hardware designers to resolve layout-driven electrical and mechanical tradeoffs

High-Speed Signal Integrity

• Route high-speed interfaces such as DDR, PCIe, Ethernet, USB, and SerDes-based links
• Apply controlled impedance routing, differential pair tuning, length matching, and return-path management
• Implement SI-aware stack-ups and routing strategies to minimise crosstalk and signal loss

High-Power & Power Integrity

• Layout high-current power paths, including VRMs, DC-DC converters, and power planes
• Optimise copper distribution, plane structures, and via arrays for current handling and low impedance
• Support thermal performance through copper pours, stitching vias, and heatsink interface planning

PCB Library Creation & Management

• Create, validate, and maintain schematic symbols, PCB footprints, and 3D models
• Ensure land patterns meet IPC standards and supplier recommendations
• Own library quality, version control, naming conventions, and release processes
• Collaborate with engineering, manufacturing, and supply chain to ensure component accuracy and lifecycle readiness
• Drive continuous improvement of library standards and documentation

Collaboration & Reviews

• Participate in schematic reviews, layout design reviews, and SI/PI discussions
• Work with SI/PI engineers to implement simulation-driven layout constraints
• Support DFM/DFA reviews and interface directly with PCB fabricators and assemblers

Manufacturing & Debug Support

• Generate manufacturing deliverables (Gerbers, ODB++, IPC drawings, pick-and-place data)
• Support board bring-up and debug by implementing layout ECOs
• Resolve layout- and footprint-related manufacturing or assembly issues

Qualifications & Experience

• Diploma, Bachelor’s degree, or equivalent experience in Electronics, Electrical Engineering, or related field
• 7+ years of professional PCB layout experience
• Proven experience with high-speed digital and high-power PCB designs
• Hands-on experience creating and maintaining PCB libraries for production hardware

Technical Skills

PCB layout tools such as Siemens Xpedition, Altium Designer, Cadence Allegro, or equivalent

• Library creation and management workflows
• High-speed routing (DDR, PCIe, Ethernet, USB, SerDes)
• High-current and power integrity layout techniques
• Multi-layer PCB stack-ups (10+ layers preferred)

Skills & Competencies

• Exceptional attention to detail and design discipline
• Strong ownership mindset for design quality and library integrity
• Effective communicator across hardware, mechanical, and manufacturing teams
• Comfortable managing multiple designs and revisions in parallel

Preferred Experience (Nice to Have)

• Experience with SI/PI simulation-informed layouts
• Familiarity with EMI/EMC-aware layout practices
• Experience with HDI, fine-pitch BGAs, and advanced PCB technologies
• Experience with AI accelerator or HPC hardware

   How we work

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is

About us

• Founded in 2022, team of 70+ which is expanding rapidly
• Modern, open offices in London and Bristol
• Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency

Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

We are looking for a highly motivated and experienced RTL Design Engineer to join our dynamic team. In this role, you will play a key part in the design and implementation of digital systems, contributing to every stage of the project lifecycle. Your work will involve developing and optimising Register Transfer Level (RTL) designs for high-performance and power-efficient systems

RTL Development and Implementation:

• Develop and maintain RTL specifications for digital designs, ensuring clarity and accuracy.
• Implement complex design modules with a focus on performance, power, and area efficiency.
• Take ownership of design tasks, including planning, execution, and delivery of work packages.
• Define design tasks for the project, including partitioning, interface specifications, and module definitions.
• Collaborate with verification engineers to ensure functional correctness through simulation and formal verification.

Cross-Functional Collaboration:

• Work closely with physical design engineers, and verification teams to ensure seamless integration of the design.

Documentation and Standards Compliance:

• Document RTL design methodologies, module interfaces, and functional requirements.
• Ensure adherence to coding standards, best practices, and maintainability guidelines.

Qualifications and Skills:

Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.

Experience:

• 6+ years of experience in digital design, RTL development, or related roles.
• Proven expertise in developing RTL designs for high-performance systems.
• Familiarity with advanced digital design concepts, such as pipelining, clock-domain crossing, and power gating.
• Experience with high-speed or low-power design methodologies.

Soft Skills:

• Strong analytical and problem-solving skills.
• Effective communication and collaboration abilities in cross-functional teams.
• A detail-oriented approach with a focus on quality and efficiency.

How we work

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is

About us

• Founded in 2022, team of 70+ which is expanding rapidly
• Modern, open offices in London and Bristol
• Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency

Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will support the implementation of complex IC physical designs, from synthesis to sign-off. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock tree synthesis (CTS), routing, and sign-off.
• Work on synthesis, timing analysis (STA), and optimisation to achieve strong PPA metrics.
• Assist in power planning and analysis, addressing IR drop, electromigration, and related effects.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Work closely with RTL and architecture teams to support design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 0–5 years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below), including internships.
• Familiarity with EDA tools for place & route, STA, and sign-off.
• Basic understanding of CMOS technology, semiconductor physics, and process limitations.
• Exposure to timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation is a plus.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Interest in working with advanced AI tools and models as part of the design workflow.
• Experience or coursework in high-performance computing (HPC), AI accelerators, or networking chips is a plus.

About Graphcore

At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

Job Summary

We are seeking a Senior Semiconductor Reliability Engineer to lead reliability strategy and execution across advanced silicon nodes and advanced packaging technologies, spanning both pre-silicon and post-silicon phases. This role is responsible for ensuring robust product reliability from technology selection and design enablement through silicon bring-up, qualification, and high-volume manufacturing.

The successful candidate will work at the intersection of device physics, circuit design, packaging, and manufacturing, providing technical leadership on reliability risk assessment, modeling, qualification, and failure analysis for complex, high-performance devices.

The Role

As a Senior Reliability Engineer, you will lead reliability strategy and qualification activities for advanced AI silicon and package technologies. You’ll work across pre-silicon analysis, post-silicon qualification, and failure analysis, partnering closely with silicon, packaging, manufacturing, and quality teams.

This role combines deep technical expertise with cross-functional leadership and offers the opportunity to influence reliability methodology for cutting-edge AI hardware platforms.

Responsibilities and Duties

• Define reliability requirements for advanced silicon nodes and package platforms
• Perform pre-silicon reliability risk assessments across silicon, interconnect, and package technologies
• Evaluate reliability mechanisms including EM, TDDB, BTI, HCI, BEOL, and silicon-package interaction
• Support design reviews, guard-banding, and reliability sign-off activities
• Develop and execute qualification plans aligned with JEDEC and customer requirements
• Lead HTOL, thermal cycling, thermal shock, and reflow qualification testing
• Drive correlation between pre-silicon modelling and post-silicon qualification results
• Lead root-cause analysis of silicon and package-related failures
• Utilize X-ray and CSAM analysis to diagnose package defects including delamination, voiding, and cracking
• Work with foundries, OSATs, and reliability labs to resolve reliability and manufacturing issues
• Author qualification reports, risk assessments, and reliability documentation
• Mentor engineers and contribute to reliability best practices and methodologies

Candidate Profile

Essential

• Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Physics, Mechanical Engineering, or related field
• 8+ years of semiconductor reliability engineering experience
• Strong understanding of silicon reliability mechanisms including EM, TDDB, BTI, and HCI
• Experience with BEOL, interconnect, and advanced package reliability
• Hands-on experience with HTOL, thermal cycling, thermal shock, and reflow testing
• Experience using X-ray and CSAM for package failure analysis
• Familiarity with JEDEC reliability standards
• Strong analytical, communication, and cross-functional collaboration skills

Desirable

• Experience with leading-edge nodes, AI accelerators, or high-performance SoCs
• Knowledge of HBM, chiplets, TSVs, micro-bumps, and 2.5D/3D integration
• Experience with wafer-level reliability or system-level stress testing
• Experience working with foundries and OSAT partners
• Technical leadership or mentoring experience

Benefits

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Applicants for this position must hold the right to work in the UK. Unfortunately at this time, we are unable to provide visa sponsorship or support for visa applications

About Graphcore

At Graphcore, we’re building the future of AI compute.

We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.

As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.

We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

Job Summary

We are looking for high-quality silicon physical design engineers to complement our existing exceptional team. We have a range of roles available with focus on those with extensive ranges of skills and experience although exceptional candidates with less experience will be considered. We want people who work collaboratively and proactively within a team focusing on collectively achieving our goals and creating the right engineering solutions. Good communication is essential, as is the ability to adapt and learn – we value the right characteristics more than specific experience.

For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to take ownership of their designs and problem solutions. You will become part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure.

The Team

The physical design team sits within the wider silicon design team which includes RTL, verification and DFT and with whom we collaborate extensively. Our work additionally involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and then to build the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC).

Responsibilities and Duties

Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs in leading-edge process technologies while meeting ambitious development schedules. Contributions are expected to span multiple areas and involve:

• using state-of-the-art EDA tools and in-house Graphcore flows to deliver final designs that are of sign-off quality
• enhancing existing flows and in-house tools/APIs to support new features and/or methodologies
• analysis and/or debugging of complex engineering problems leading to workable solutions
• developing an understanding of emerging technical issues and applying that knowledge to optimise in-house flows and methodologies

Candidates will be expected to work closely both with other teams within Graphcore and with 3rd party support engineers/contractors, ensuring good communication between all parties, and to contribute meaningfully to the overall efficiency and success of the Physical Team.

Candidate Profile

Essential Skills and Experience:

• A Degree in Electronic/Electrical Engineering, Computer Science or related subject
• Be highly motivated, a self-starter, and a team player
• Enjoy taking responsibility and improving skills and knowledge
• Excellent problem-solving skills for debugging issues seen and finding root causes
• Ability to program/script (required to solve design issues, typically in Tcl and Python)
• Experience in 7nm or smaller technologies
• A good breadth of experience with physical design flows including: Floorplanning/Budgeting, Synthesis, Place and Route, Clock CTS, Timing Analysis, Logical Equivalence, Physical Verification (DRC/LVS/ERC)

Desirable Skills and Experience:

• In depth expertise in one or more aspects of physical design flows
• Structuring of builds to maximise PPA
• Silicon transistor knowledge including std cell libraries and/or memories
• 2D and 3D design (CoWoS, UCIe etc.)
• High speed, high power and/or full reticle chip design
• Ethernet, PCIe, LPDDR, HBM interfaces
• Power integrity and optimization
• 2nm or 3nm technologies
• Chip finishing (pad rings, chip level LVS/DRC/ERC)
• Design for test
• Team management
• Project Planning

Benefits

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments

About Graphcore

At Graphcore, we’re building the future of AI compute.

We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.

As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.

We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

The Person 

Graphcore’s experienced, skilled, and motivated engineering team is heavily involved in shaping the future of AI. A successful candidate will exhibit exceptional knowledge in Design for Testability (DFT) and will have a strong technical background and experience in DFT methodologies, complemented by a robust, self-motivated work ethic. The ideal candidate should also have a focus on quality and demonstrate a good understanding of the importance of production test on the success of a product. Some hands-on experience in one or more of the following areas is essential: RTL design, simulations and debugging, synthesis, STA.  

The Role: 

We are expanding and looking for an experienced DFT engineers to join the Silicon team. As a part of our team, you will have the opportunity to work on next-generation AI designs targeted for data centers applications. 

Responsibilities: 

• Keep up with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies 

• Work closely with design, verification, physical design and product engineering teams to integrate DFT requirements into the overall design process 

• Define and implement DFT architecture and features for next-generation AI designs and support their verification effort 

• Develop efficient DFT flows and methodology compatible with silicon design flows 

• Work with 3rd party IPs to integrate the provided design into the DFT infrastructure 

• Generate structural test vectors, analyze and improve test coverage 

• Work with the product and test engineering teams to ensure successful silicon bring-up and help identify any silicon failures to enhance yield learning and improvement 

Requirements: 

• Very good understanding of DFT components like JTAG (IEEE 1149.x), IJTAG (IEEE P1687), Core Test (IEEE P1500), SSN (Streaming Scan Network), Test Compression, OCC etc. 

• Experience on developing DFT specifications and driving the implementation of the DFT features 

• Experience in MBIST and BISR implementation and verification is desired 

• Solid understanding of design verification methodologies for validating the DFT features using simulation in pre-silicon designs 

• Exposure to STA constraints development and analysis for DFT modes and SDF simulations would be a plus 

• Experience in Scan based testing and industry standard ATPG tools 

• Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other EDA tools 

• Very good knowledge of Digital Integrated Circuits and Systems 

• Hands-on experience with Verilog RTL coding and familiarity with System Verilog   

• Strong scripting and debugging skills using programming languages like Python, TCL, Perl, Shell etc. 

• Exposure to silicon bring-up, post-silicon testing and tester pattern debugging 

• Strong problem-solving skills across various levels of design hierarchies 

• Great team working and communication skills 

Academic Credentials 

• Bachelors or Masters or PhD in Computer engineering/Electrical engineering/Electronics Engineering

Benefits: 

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments  

We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know.