Principal Embedded SW/FW Engineer (Bringup) - Bengaluru, multiple vacancies 

Job Summary

We have an exciting opportunity to be part of a collaborative, cross-functional development team validating cutting-edge, high-performance AI chips and platforms.

 You will play a key role in supporting new product introductions and post-silicon validation.

Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to provide technical guidance to other engineering team members. In this role, you can leverage our experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes.

The Team

The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team.

Responsibilities and Duties

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon
• Deploy silicon validation tests on first silicon and debugging them
• Develop automated test framework and regression test suites in Python to optimize validation efficiency
• Collaborate closely with engineers from many other disciplines on a variety of topics
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies
• Analyse test results, identify and debug failures/defects
• Contribute to shared test and validation infrastructure
• Provide feedback to architects

Candidate Profile 

Essential:

• Understanding of ML applications and their workloads
• A self-starter who can apply independent judgement
• A team player able to lead and support colleagues with difficult concepts
• Strong experience in Bare metal / embedded C/C++

• Excellent problem-solving, analytical & diagnostic skills

• Ability to work across teams and programming languages to find root causes of critical and complex issues

• Experience of the post-silicon validation process applied in digital ASIC environments

• Python, Linux

• Excellent communication skills and the ability to explain difficult concepts to resolve issues 

Desirable

• 10+ years  experience 
• Experience building and leading, multi-site teams
• Driver level experience with one or more of the following is highly desirable:

• PCIe
• Ethernet
• Memory technologies (LPDDR, DDR, HBM, …)
• Other peripherals such as I2C, I3C, SPI, …

• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable.
• Experience of Arm CPUs, System IP and debug tools.
• Experience of AMBA protocols.
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, 

Staff Embedded SW/FW Engineer (Bringup)

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.

Job Summary

We have an exciting opportunity to be part of a collaborative, cross-functional development team developing C code used to validate cutting-edge, high-performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation.

Working within the Post-Silicon Bringup team, you will be involved with bringing first silicon to life, developing code primarily in C to configure and exercise systems and sub-systems on new silicon devices, and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes.

The Team

The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. 

Responsibilities and Duties

• Plan, design, develop and debug silicon bringup sequences and test in bare metal C/C++ on FPGA/Emulator prior to first silicon
• Deploy configuration sequences and validation tests on first silicon and debug them
• Develop automated test framework and regression test suites in Python to optimize validation efficiency
• Collaborate closely with engineers from many other disciplines on a variety of topics
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies
• Analyse test results, identify and debug failures/defects
• Contribute to shared test and validation infrastructure
• Provide feedback to architects

Candidate Profile

Essential:

• Strong experience in Bare metal / embedded C/C++
• Good knowledge of digital ASICs.
• Be highly motivated, a self starter, and a team player 
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the post-silicon validation process applied in digital ASIC environments
• Python, Linux
• Excellent communication skills and the ability to collaborate with others to solve problems.
• Excellent problem-solving, analytical & diagnostic skills

Desirable:

• Driver level experience with one or more of the following is highly desirable:

• PCIe
• Ethernet
• Memory technologies (LPDDR, DDR, HBM, …)
• Other peripherals such as I2C, I3C, SPI, …

• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable.
• Experience of Arm CPUs, System IP and debug tools.
• Experience of AMBA protocols.
• Understanding of ML applications and their workloads.
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

HFT Software Developer – Junior & Senior Levels

About DeepFin Research

DeepFin Research is a proprietary high-frequency trading (HFT) firm powered by cutting-edge Deep Learning (DL) and Deep Reinforcement Learning (DRL). We've brought on teammates from Nvidia, DeepMind, CitSec, Graviton, Tower, Jump, and others, and are aggressively working across cutting edge AI research and traditional quant research methods to monetise our AI generated signals across the global financial markets.

The Role

We are looking for exceptional HFT software engineers to build our HFT trading infrastructure across global finanacial markets, including different asset classes, end-to-end from the ground up. This will include working across connectivity, market data, execution, risk, and building high performance high throughput C++ systems.

Responsibilities

• Design, implement, and optimize ultra-low-latency, zero-allocation trading engines in modern C++.
• Develop and maintain market data handlers and execution gateways utilizing protocols like FIX, OUCH, ITCH, and raw UDP multicast.
• Optimize system critical paths through OS-level tuning, CPU pinning, cache-line optimization, and NUMA-aware programming.
• Interface with hardware-accelerated components, working alongside FPGA engineers to integrate PCIe/DMA data pipelines.
• Implement kernel-bypass networking solutions (e.g., Solarflare OpenOnload, DPDK) to minimize network stack latency.
• Collaborate directly with AI researchers and quantitative traders to deploy complex quantitative models into strict, latency-sensitive production environments.
• Work end-to-end on projects from the ground up – this is not a role to focus on specialised parts of the infrastructure stack, but rather to see projects through end-to-end.

Ideal Candidate Profile

• 1–3 years of experience in low-latency software engineering for Junior candidates; 3–10+ years for Senior candidates.
• Exceptional expertise in C++ with a deep understanding of lock-free data structures, custom memory allocators, and hardware architecture.
• Proven experience building systems in HFT or highly concurrent, real-time computing environments.
• Strong grasp of Linux internals, network programming (TCP/IP, UDP), and performance profiling tools (e.g., perf, VTune).
• Solid understanding of futures markets microstructure; exposure to FX and options markets is a strong plus.
• Entrepreneurial mindset with the communication skills required to thrive in a fast-paced, highly collaborative environment, preferring end-to-end ownership over extreme specialization.

HFT Quantitative Developer

About DeepFin Research

DeepFin Research is a proprietary high-frequency trading (HFT) firm powered by cutting-edge Deep Learning (DL) and Deep Reinforcement Learning (DRL). We've brought on teammates from Nvidia, DeepMind, CitSec, Graviton, Tower, Jump, and others, and are aggressively working across cutting edge AI research and traditional quant research methods to monetise our AI generated signals across the global financial markets.

The Role

We are looking for exceptional quantitative developer with outstanding expertise at the intersection of quantitative research and C++ development to focus both on simulation and productionisation. This will include designing and building simulation across various financial markets, and taking high-frequency and mid-frequency alpha turning it into scalable, production-grade PnL across global exchanges.

Key Responsibilities

• Productionise research models into high-performance C++ systems used for live trading across multiple futures exchanges.
• Integrate and process L3/order-book data at scale, building and maintaining parsers, normalised book structures, and data pipelines.
• Develop and optimise execution logic, order placement strategies, queue-positioning logic, microstructure-aware order types, and latency-sensitive workflows.
• Collaborate closely with quant researchers to understand signals, model assumptions, and expected behaviours, ensuring seamless transition from prototypes into production code.
• Work with infra/engineering teams to deploy, monitor, and refine strategies in live environments; diagnose latency bottlenecks, instability, and performance drift.
• Build and maintain simulation/backtesting tools for microstructure-accurate evaluation of execution behaviour.
• Optional (desirable): support vol surface modelling, options execution logic, and cross-asset HFT monetisation.

Required Experience & Skills

• Must have Experience in HFT market making. 
• Outstanding C++ and Python expertise.
• Experience working with L3 and order-book data, market-data adapters, and high-throughput feed handling.
• Experience productionising HFT or mid-frequency strategies in live environments.
• Understanding of market microstructure: queue dynamics, adverse selection, order types, latency paths, tick-rule details.
• Ability to operate across both research and engineering disciplines: reading model code, understanding signals, and implementing robust production systems.
• Options experience is desirable
• FPGA experience is desirable