Job Summary

We are seeking a talented Signal Processing Engineer to design, develop, and optimize advanced digital signal processing (DSP) algorithms for on-chip and embedded implementation. In this role, you will create efficient, hardware-friendly algorithms that run directly on custom SoCs, enabling real-time processing with constraints on power, latency, area, and throughput. You will collaborate closely with the SoC, Firmware, and Machine Learning teams to translate high-level signal processing needs into production-ready solutions.

Key Responsibilities

• Design and develop signal processing algorithms for sensing neural activity in the cortex (e.g. spike detection), monitoring cortical electrode health, and more.
• Design and develop numerical algorithms, such as custom data compression to increase radio throughput.
• Develop fixed-point or quantized versions of algorithms optimized for constrained hardware.
• Implement and verify algorithms in high-level languages and transition them to hardware-friendly representations.
• Perform algorithm-to-architecture mapping: analyze trade-offs between accuracy, latency, power, and resource utilization on the SoCs.
• Collaborate with the digital design team to define micro-architectures for custom on-chip processing pipelines, including dataflow, pipelining, and parallelization.

Required Qualifications

• Education: BS, MS or PhD in Electrical Engineering, Computer Engineering, Signal Processing, or a related field.
• Experience: 3+ years in digital signal processing algorithm development or real-world products, with a focus on embedded or hardware-constrained implementations.
• Fluent in signal processing fundamentals (both analog and digital) and strong numerical capabilities.
• Familiarity with fixed-point arithmetic, quantization effects, and numerical precision trade-offs.
• Proficiency in Python and C for algorithm prototyping and simulation.

Preferred Qualifications

• Hands-on experience with Verilog/VHDL, or transitioning algorithms to RTL.
• Experience with dedicated DSP cores or accelerators.
• Track record of optimizing for power/area/latency in resource-constrained environments.

Base Salary Range:

 $121,000 - $230,500

This role entails design and development of scalable infrastructure and software for the verification of high performance CPUs going into industry leading AI/ML architecture. The successful candidate will be responsible for development and automation of many aspects of the verification environment. The person coming into this role will have opportunities such as: writing low-level RISC-V assembly, building complex low-latency multithreaded testbenches, database programming, software testing and release automation, verilog coding and optimization of CPU components, and contributing to open source projects in the RISC-V ecosystem.

This role is on site, based out of Santa Clara, CA or Austin, TX.

This is for our Fall 2026 Semester

Responsibilities:

• Build software and scripts for high performance simulation and emulation of CPUs
• Improve verilog for optimal simulation performance and fpga emulation synthesis
• Maintain and enhance the Git infrastructure to support CI/CD, nightly regressions across multiple development platforms
• Build software tools and scripts for design flow automation

Experience & Qualifications:

• Currently working towards a Bachelors program
• Strong programming skills. C++, Python, SystemVerilog preferred.
• Solid experience with the Linux operating system
• Experience with version control. Git preferred.
• Interest in CPUs, hardware design, and/or programming
• Willing to learn and adapt

The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Santa Clara, CA or Austin, TX

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a BS/MS/PhD in EE/ECE/CE/CS with 5+ years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs.
• You are fluent in Verilog RTL for DFT logic (lock-up latches, clock gates, scan anchors) and comfortable with SystemVerilog/UVM.
• You have hands-on experience with ATPG and DFx insertion tools, fault models (Stuck-at, Transition, Path Delay, IDDQ, Cell-Aware), and low-power design flows.
• You bring strong debug and problem-solving skills across design hierarchies and collaborate effectively with design, PD, verification, and test teams.

What We Need

• Implement and integrate DFT features (scan, JTAG, compression, ASST, MBIST) into RTL from early design through tapeout across multiple IPs.
• Own ATPG, test coverage analysis, and gate-level simulation (e.g., with Synopsys VCS/Verdi) to achieve and maintain high-quality test coverage.
• Plan, implement, and verify MBIST, and work closely with Test Engineering on test planning, pattern delivery, and debug.
• Develop and refine DFx flows and methodology that integrate cleanly with front-end and physical design flows, balancing coverage, test cost, and design intrusiveness.

What You Will Learn

• How to drive DFT for industry-leading AI/ML architectures, working on high-performance chips with aggressive performance and power targets.
• Practical strategies to reduce test cost while maintaining coverage, and to design DFT hooks that accelerate silicon bring-up and yield learning.
• How to minimize DFT intrusions while integrating cleanly with RTL, verification, physical design, and production test flows.
• How a senior, cross-functional ASIC team collaborates across design, PD, verification, and manufacturing to achieve first-pass silicon success on advanced nodes.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.

This role is hybrid, based out of Austin, TX, Fort Collins, CO or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced micro-architect who thrives in building CPU systems (multiple cores, multiple clusters of cores and subsystem components) from scratch.
• Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
• Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

What We Need

• 10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
• Collaborate closely with DV, PD, architecture and performance engineers to meet functional, timing, and power goals.
• Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
• Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
• Enhance RTL design environment, tools, and methodologies to improve development efficiency.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• How to design and optimize a custom RISC-V CPU system from first principles.
• Integration of open-source and industry-standard tools to improve RTL flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Staff Design for Test STA Engineer at Tenstorrent, you will be a key technical leader in ensuring the testability, quality, and performance of our next-generation AI processors. This role requires a good understanding of both Design for Test (DFT) architecture and implementation, as well as comprehensive expertise in Static Timing Analysis (STA) for complex SoCs. You will be responsible for defining and implementing the full DFT methodology for our high-speed, multi-core designs, owning the top-level timing constraints and sign-off for all DFT modes, and collaborating closely with RTL, Physical Design, and Product Engineering teams to achieve first-pass silicon success.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Deep knowledge of core DFT concepts including Scan Compression and insertion, Memory BIST and repair schemes, JTAG/IJTAG, and at-speed test methodologies.
• Comprehensive understanding of Clock Domain Crossings (CDC), Reset Domain Crossings (RDC), timing sign-off modes and constraints, and proficiency in using industry-leading Static Timing Analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus etc).
• Deep knowledge of DFT specific timing modes including JTAG, Scan Shift, Scan Slow Capture, Scan Fast Capture, Memory BIST etc.
• Experience in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification.

What We Need

• Coordinate DFT requirements across SOC, IP and product teams and work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
• Lead the definition, generation, and validation of comprehensive DFT timing constraints (SDC) to ensure timing closure for all test modes (e.g., Scan, JTAG, Memory BIST).
• Own the STA sign-off for DFT modes at both the block and top-level, including corners and operating conditions, using industry-standard tools (e.g., PrimeTime, Tempus etc).
• Work closely with the Physical Design team (Synthesis, P&R) to drive timing convergence, resolve complex timing violations, and generate necessary timing ECOs.
• Identify and implement improvements to existing DFT and STA flows, enhancing efficiency and robustness.
• Participate in ATE targeted test patterns, validation and silicon- debug
• Work closely with test and product engineering teams on silicon characterization and validation.

What You Will Learn

• Advanced Design for Test (DFT) methodologies for cutting-edge AI processor architectures, including comprehensive scan insertion, Memory BIST, and at-speed test strategies
• In-depth Static Timing Analysis (STA) techniques for complex multi-core SoCs, mastering industry-standard tools like PrimeTime and Tempus to ensure timing closure across diverse operational modes
• Sophisticated cross-functional collaboration skills, working seamlessly with RTL, Physical Design, and Product Engineering teams to drive first-pass silicon success
• Innovative problem-solving approaches for resolving complex timing violations and optimizing test flows in high-performance semiconductor design environments

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we are building open, state of art compute for AI and RISC‑V CPUs. You will lead the technical efforts and strategy around our existing emulation infrastructure for high‑performance CPUs that power these products. Your work will directly enable silicon bring‑up, validation, and customer‑ready systems.

This role is hybrid, based out of Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have strong background in CPU verification, emulation, and debug.
• You are fluent in Verilog and SystemVerilog for complex SoC designs.
• You are a technical leader who drives complex debug efforts, solves ambiguous technical problems, and mentors younger engineers.
• Experience with Zebu emulation platforms is a significant plus.
• You collaborate closely with design, verification, and vendors to move fast and unblock teams.

What We Need

• Lead the technical strategy and execution to scale and optimize existing emulation infrastructure on commercial and open‑source platforms.
• Enable the emulation infrastructure and workflow, including producing reliable emulation builds.
• Drive and lead complex cross-functional debug and root cause analysis efforts.
• Optimize emulation performance and regression flows with Design Verification teams and tool vendors.

What You Will Learn

• How to bring state of art AI and CPU architectures to life on emulation.
• How to design large‑scale emulation regressions that mirror real customer workloads.
• How to tune emulation performance across different vendors and hardware platforms.
• How open hardware and software come together across Tenstorrent’s full compute stack.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

RISC-V CPU RTL owner will play a key role in developing next-generation CPU design. This position requires a deep understanding of CPU design including Architecture, RTL, Design Verification, Physical Design Flow. The ideal candidate will drive the unit specification, RTL design, and unit verification.

This role is Remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Key Responsibilities:

• RISC-V CPU Unit Microarchitecture Specification: Define and develop microarchitecture specifications for the assigned unit (branch predictor, rename, instruction scheduling, vector execution, load/store, vector load/store support). The specification includes not only design, but also comprehensive analysis / strategy for verification and PPA (power, performance, area) closure.
• RISC-V CPU Core Unit RTL Design: The candidate will be responsible for the quality of RTL including design verification and PPA closure. This includes writing RTL, reviewing / refining unit verification environment, applying right RTL optimization to control PPA.
• AI Assisted Design Adaption: To maximize the team’s output, the candidate actively uses AI tools to accelerate the CPU design process.
• Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor junior members in the team.

Qualifications:

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Proven track record of designing high-performance CPU RTL for x86, Arm, POWER, SPARC, or RISC-V.
• Deep understanding of design verification strategy and trade-offs for verification methodology (simulation, formal, various checkers, etc…)
• Deep understanding of CPU microarchitecture and PPA trade-off.
• Basic understanding of RISC-V Architecture including V-extension is preferred.
• Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog or VHDL.
• Excellent problem-solving abilities and analytical skills.
• Strong communication skills, with the ability to convey complex technical concepts to diverse audiences.
• Ability to work collaboratively in a team-oriented environment and across multiple disciplines.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.

This role is hybrid, based out of Bengaluru, India.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced micro-architect who thrives in building CPU systems (multiple cores, multiple clusters of cores and subsystem components) from scratch.
• Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
• Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

What We Need

• 10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
• Collaborate closely with DV, PD, architecture and performance engineers to meet functional, timing, and power goals.
• Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
• Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
• Enhance RTL design environment, tools, and methodologies to improve development efficiency.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• How to design and optimize a custom RISC-V CPU system from first principles.
• Integration of open-source and industry-standard tools to improve RTL flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Optiver’s hardware research, development, and manufacturing team, based in Austin, builds some of the world’s fastest and most competitive trading systems. As we continue to grow, we’re looking for a software engineer to help develop the OS and software that powers our custom hardware.

This role spans everything from low-level hardware integration to collaborating with infrastructure teams that manage production systems and traders who configure them to fit their specific needs. While we primarily use Python and Linux, you’ll also encounter a diverse tech stack including TCL, C, C++, ASM, VHDL, and DSLs across platforms from x64 servers to embedded cores.

What you’ll do:

As Software Engineer, your key responsibilities include:

• Designing and maintaining the OS and software stack behind our trading hardware
• Building and supporting Python-based interface layers to control and monitor hardware systems
• Developing software for STM processors embedded on prototype boards
• Managing and supporting a fleet of hardware systems in a live production environment
• Collaborating closely with hardware, infrastructure, and trading teams to ensure seamless system performance
• Contributing to infrastructure automation and transitioning into embedded development and low-level hardware logic over time

What you’ll get:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• Strong foundation in computer science fundamentals and hardware systems
• Proficiency in Python, including familiarity with relevant libraries and APIs
• Experience writing software in C/C++
• Creative problem-solving skills at the system level
• Ability to collaborate with developers and researchers

Nice to have:

• Experience with low-level hardware/software interactions (drivers, buses, pins, registers, etc.)
• Ability to read and interpret datasheets and electrical engineering schematics
• Familiarity with devices and drivers in Linux
• Experience with FPGA design using VHDL/Verilog and the Vivado suite of tools
• Knowledge of communication protocols, especially Ethernet
• Exposure to network equipment operating systems like Cisco IOS, Arista EOS, or Juniper MOS
• Experience working with high-performance trading network hardware (both packet- and circuit-switched)

Who we are:

At Optiver, our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency, and stabilising the market no matter the conditions. With a focus on continuous improvement, we prioritise safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

Efficient is looking for a seasoned Design Verification & Emulation Manager to staff, lead and scale our verification and emulation organization which is part of our newly formed HW engineering organization. This is a high-impact leadership role responsible for ensuring silicon correctness and system-level readiness across multiple industry defining product lines. You will own the verification strategy from block-level to full-chip, drive emulation-based validation for early software enablement, and build a world-class team of verification and emulation engineers.

This role combines deep technical expertise with strong people leadership and program execution skills, and is ideal for someone who thrives at the intersection of architecture, verification methodology, hardware-software integration, and team building. This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.  Join our team and help us shape the future of computing at the edge and beyond! 

Key Responsibilities 

• Define end-to-end verification strategy from block-level through full-chip simulation to emulation and prototyping
• Own UVM-based methodology, including constrained-random, coverage-driven closure, assertions, and formal verification adoption
• Drive emulation platform strategy — platform selection, capacity planning, compilation flows, and multi-project scheduling
• Enable system-level validation on emulation — processor boot, OS bring-up, firmware execution, and IO exercising
• Deliver pre-silicon platforms for early software development in partnership with firmware and software teams
• Establish hybrid simulation-emulation methodologies using transactor-based interfaces to maximize both environments
• Own functional coverage models and sign-off criteria, driving closure across simulation and emulation combined
• Lead debug and root cause analysis across simulation and emulation, driving cross-functional bug resolution
• Manage verification dashboards, bug tracking, and regression health to provide clear visibility to program leadership
• Build, mentor, and scale a high-performing team of verification and emulation engineers
• Drive verification schedules and risk mitigation aligned with chip program milestones and tapeout readiness
• Represent verification and emulation in tapeout readiness reviews and program-level decision forums
• Collaborate cross-functionally with Compiler Team, RTL design, architecture, DFT, physical design, and post-silicon teams
• Manage emulation lab infrastructure, including hardware resources, licensing, and vendor relationships
• Evaluate and adopt new EDA tools and methodologies, including AI/ML-assisted verification techniques.
• Define right DV  mix for in-house  vs outsourcing to 3rd party vendors. Coordinate 3rd party vendor resources towards achieving project goals.

Required Qualifications & Experience 

• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. PhD is a plus.
• Experience: 12+ years of progressive experience in ASIC/SoC design verification, with at least 3–5 years in a management or senior technical leadership role overseeing both verification and emulation functions.
• Verification Methodology: Deep expertise in UVM, constrained-random verification, functional coverage, assertions (SVA), and simulation-based debug. Strong understanding of formal verification techniques.
• Emulation Platforms: Hands-on experience with at least one major emulation platform (Palladium, ZeBu, or Veloce) and familiarity with FPGA prototyping flows.
• Languages & Tools: Strong proficiency in SystemVerilog, Verilog, and C/C++ for testbench and reference model development. Experience with Python, Tcl, and scripting for flow automation.
• SoC Architecture: Solid understanding of modern SoC architectures — processors (ARM, RISC-V), cache coherency, interconnects (AMBA AXI/ACE/CHI), memory subsystems, and common peripherals.
• Leadership: Demonstrated ability to build, mentor, and manage verification teams of 10+ engineers. Experience hiring, developing talent, and scaling teams.
• Execution: Strong track record of driving verification closure and tapeout sign-off on complex designs (multi-million gate, multi-clock domain, multi-power domain).

Preferred Qualification

• Experience with portable stimulus standard (PSS / Accellera) for verification reuse across simulation and emulation.
• Background in power-aware verification (UPF/CPF-based) and low-power design verification challenges.
• Experience with AI/ML-assisted verification techniques (e.g., intelligent coverage convergence, ML-driven regression optimization).

We offer a competitive salary for this role, generally ranging from $210,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

DESIGN VERIFICATION ENGINEER

AUSTIN, TX

We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities​:

• Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems

• Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards

• Collaborate with software teams to define and implement configurable testbenches

• Work with design teams test plans, failure debug, coverage, etc.​

Qualifications and Preferred Skills​

• BS, MS in Electrical Engineering, Computer Engineering or Computer Science

• 8+ years and current hands-on experience in block-level/IP-level/SoC-level verification

• Proficiency in Verilog, SystemVerilog

• Familiarity with industry-standard EDA tools for simulation and debug

• Deep experience with UVM-based testbenches

• Experience with modern programming languages like Python

• Knowledge of Arm AMBA protocols such as AXI, APB, and AHB

• Understanding of Arm CHI protocol is a plus

• Experience on working with IP's for caches, cache coherency, memory subsystems, interconnects, and NoC's

• Experience with formal verification techniques, emulation platforms is a plus

• Excellent problem-solving skills and attention to detail

• Strong communication and collaboration skills

rich.goldstein@bayasystems.com

 What you need 

We're seeking passionate technologists who thrive on pushing the boundaries, solving complex challenges, and driving transformative solutions. 

At Ambiq, you'll collaborate with a dynamic team that values relentless innovation, customer-centric thinking, and continuous learning. If you're a self-motivated, creative problem-solver eager to push technological limits and make a meaningful impact in energy efficiency, this is your opportunity to grow, excel, and turn groundbreaking ideas into reality. 

Most importantly, the successful candidate will be able to live the Ambiq Shared Values: 

• Innovate: We tenaciously find ways to break down the barriers to possible solutions 
• Collaborate: We proactively communicate and encourage each other to be better. 
• Focus: We keep the voice of the customer at the center of everything we do. 
• Learn: We strive for continuous improvement and are always curious. 
• Achieve: We execute on quality and follow through on our commitments.