About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

Job Summary 

We are seeking an experienced Staff UEFI Engineer to design, develop, and deploy UEFI-based firmware for Graphcore’s hyperscale AI server platforms. 

This role focuses on developing system firmware responsible for platform initialization, hardware configuration, and reliability features across large-scale data center deployments. 

The Team 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

The Firmware Engineering team develops the foundational firmware responsible for platform initialization, hardware configuration, and system reliability across Graphcore’s AI compute infrastructure. 

The team collaborates with silicon engineering, hardware design teams, BMC firmware teams, validation engineers, and platform architects to enable reliable server platform bring-up and operation. 

Responsibilities and Duties 

• Design, develop, and deploy UEFI-based firmware for hyperscale server platforms. 

• Collaborate with ODM partners throughout the design lifecycle from concept to mass production. 

• Integrate UEFI firmware into CI/CD pipelines enabling automated builds, regression testing, and static analysis. 

• Develop firmware functionality supporting platform initialization including CPU, memory, PCIe, and system interconnects. 

• Implement system firmware security features including root of trust, secure boot chains, and signed firmware updates. 

• Develop platform firmware features supporting server reliability, availability, and serviceability (RAS). 

• Build firmware interfaces supporting telemetry, firmware updates, and system management capabilities. 

• Collaborate with hardware, BMC, security, and validation teams to ensure full platform integration. 

• Debug and perform root cause analysis for firmware and hardware issues across lab and production environments. 

Candidate Profile 

Essential 

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. 

• 10+ years of experience developing UEFI or BIOS firmware for server platforms. 

• Strong expertise with UEFI, TianoCore, and firmware architecture design. 

• Experience developing firmware solutions for hyperscale or cloud data center environments. 

• Strong programming skills in C/C++. 

• Deep understanding of DDR memory training, cache coherency protocols, and PCIe subsystems. 

• Strong knowledge of server platform architecture including power delivery, thermal management, sensors, and FRUs. 

• Experience implementing CI/CD pipelines for firmware development. 

• Experience debugging system firmware using logic analyzers, JTAG, GDB, and similar tools. 

Desirable 

• Experience developing UEFI firmware for ARM-based server platforms. 

• Experience with EDK II codebase development and upstream contribution. 

• Experience working with ODM/JDM partners on server platform development programs. 

• Experience delivering firmware for hyperscale cloud deployments and production environments. 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

The Team

This role can sit in our NYC HQ on a hybrid basis, or it can be fully remote while working from a location based in either Eastern or Central time zones. We are looking for an experienced Senior Engineer for our SRE, Atlas team to support, maintain and grow the Atlas platform. As a senior SRE, you will be expected to be able to design & build complex systems, operate with autonomy and act as owner for everything you do. 

The SRE Atlas team works alongside the various Atlas software engineering teams to provide expertise about running systems at scale, build new tooling and automation and perform essential maintenance of the Atlas fleet. 

This is an SRE team, which means you can expect a highly hands-on approach, tackling the technical challenges of implementing large scale solutions that have the ability to impact our customer’s most crucial workloads. 

Role Overview

We are seeking a talented Site Reliability Engineer (SRE) with a strong infrastructure background. This role requires engineers to have a customer-first mindset to ensure that everything we do results in a stronger product and a better experience for all Atlas customers. 

The ideal candidate should

• Have 5+ years of experience running critical systems at scale
• Value efficiency in processes and operations, and display a preference for automation over manual processes (“allergic to ops work”)
• Be familiar with a major cloud provider (AWS, Azure, or GCP) and possess the ability to build and operate systems in a multi-cloud environment
• A strong understanding of how to run a large scale Linux environment, including low level fundamentals 
• Firm grasp of at least one modern programming language, beyond basic scripting (Go, Ruby, Python)
• Solid understanding of web and network protocols and standards (HTTP, TLS, DNS, etc)

Special Requirements:

• Be a US Citizen

Expectations

• Participate in the development of a reliable and resilient multi-cloud platform that hosts business critical applications for a wide & varied range of customer applications
• Collaborate with service-owning teams to provide internal support, solve technical challenges and adapt or build tooling to solve novel use cases in a generic fashion
• Participate in a 24/7 on-call rotation to swiftly resolve issues related to any disruption of our customer facing Atlas fleet, ensuring minimal disruption and high availability

About MongoDB

MongoDB is built for change, empowering our customers and our people to innovate at the speed of the market. We have redefined the database for the AI era, enabling innovators to create, transform, and disrupt industries with software. MongoDB’s unified database platform—the most widely available, globally distributed database on the market—helps organizations modernize legacy workloads, embrace innovation, and unleash AI. Our cloud-native platform, MongoDB Atlas, is the only globally distributed, multi-cloud database and is available across AWS, Google Cloud, and Microsoft Azure.

With offices worldwide and nearly 60,000 customers—including 75% of the Fortune 100 and AI-native startups—relying on MongoDB for their most important applications, we’re powering the next era of software.

Our compass at MongoDB is our Leadership Commitment, guiding how and why we make decisions, show up for each other, and win. It’s what makes us MongoDB. 

To drive the personal growth and business impact of our employees, we’re committed to developing a supportive and enriching culture for everyone. From employee affinity groups, to fertility assistance and a generous parental leave policy, we value our employees’ wellbeing and want to support them along every step of their professional and personal journeys. Learn more about what it’s like to work at MongoDB, and help us make an impact on the world!

MongoDB is committed to providing any necessary accommodations for individuals with disabilities within our application and interview process. To request an accommodation due to a disability, please inform your recruiter.

MongoDB, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type and makes all hiring decisions without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.

Req ID: 426187

We are looking for an experienced Senior or Staff Engineer for our SRE, InfraSec team, to guide the security of our cloud-based infrastructure. As a Staff SRE, you will be very hands-on technically while also mentoring a small team of SREs.

The InfraSec team collaborates closely with other engineering teams to ensure that our infrastructure adheres to the highest security standards. They build essential security infrastructure and implement controls that reinforce the platform’s security posture.

This is an SRE team, which means you can expect a highly hands-on approach, tackling the technical challenges of implementing large scale solutions.This team is deeply involved in the technical aspects of security and the nuances of its actual implementation.

This role can sit in our New York City, Austin, Seattle or San Francisco offices on a hybrid basis, or it can be fully remote while working from a location based in either Eastern or Central time zones.

Responsibilities:

Cloud Security Design and Implementation:  

• Help lead the design and deployment of security solutions for cloud platforms (AWS, Azure, GCP), including network and compute security, identity management, and cloud security posture management (CSPM)

Automation and Monitoring:  

• Build automated solutions for real-time security monitoring, logging, and alerting in cloud environments. Leverage native cloud services and third-party tools for runtime security monitoring and anomaly detection

Security Tooling:

• Evaluate, implement, and manage cloud-native security tools and platforms for endpoint security, identity management (IAM), and CSPM 

Qualifications:

Experience:  

• 6+ years of experience in SRE, infrastructure engineering or similar role, with a strong focus on security work, with ideally 2+ years in a senior or staff engineering role

Security Mindset:

• A comprehensive understanding of all facets of cloud environment security, spanning from foundational OS networking layers to cloud provider configurations. Proven experience in leading projects within security-focused areas, such as runtime scanning, security observability, CSPM, and more

Cloud Expertise:  

• Strong experience with at least one cloud platform (AWS, Azure, GCP), including expertise in IAM, VPC networking, security groups, and cloud security tools (e.g., GuardDuty, Security Hub, CloudTrail)

Coding/Automation:  

• Proficiency in at least one programming language (we use Golang but are language agnostic when it comes to hiring ) and experience with infrastructure-as-code tools (Terraform, CloudFormation, Ansible) to automate security configurations and processes

Linux and Networking

• Understanding of the underlying Linux and networking concepts, including low-level fundamentals, and how they work together in complex systems

Communication and Leadership Skills:  

• Strong ability to explain complex security concepts to both technical and non-technical teams. Ability to lead a small technical team and ensure success both meeting the team goals as well as personal growth for all team members

About MongoDB

MongoDB is built for change, empowering our customers and our people to innovate at the speed of the market. We have redefined the database for the AI era, enabling innovators to create, transform, and disrupt industries with software. MongoDB’s unified database platform—the most widely available, globally distributed database on the market—helps organizations modernize legacy workloads, embrace innovation, and unleash AI. Our cloud-native platform, MongoDB Atlas, is the only globally distributed, multi-cloud database and is available across AWS, Google Cloud, and Microsoft Azure.

With offices worldwide and nearly 60,000 customers—including 75% of the Fortune 100 and AI-native startups—relying on MongoDB for their most important applications, we’re powering the next era of software.

Our compass at MongoDB is our Leadership Commitment, guiding how and why we make decisions, show up for each other, and win. It’s what makes us MongoDB. 

To drive the personal growth and business impact of our employees, we’re committed to developing a supportive and enriching culture for everyone. From employee affinity groups, to fertility assistance and a generous parental leave policy, we value our employees’ wellbeing and want to support them along every step of their professional and personal journeys. Learn more about what it’s like to work at MongoDB, and help us make an impact on the world!

MongoDB is committed to providing any necessary accommodations for individuals with disabilities within our application and interview process. To request an accommodation due to a disability, please inform your recruiter.

MongoDB, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type and makes all hiring decisions without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.

Req ID: 1263064630

We are hiring an experienced Security Software Engineer (Staff or Senior) for our Infrastructure Security team to design and build scalable security controls and services within MongoDB Atlas multi-cloud infrastructure.

The team sits within the Site Reliability Engineering organization and works with other engineering teams to ensure that our infrastructure adheres to the highest security standards.

This role can be based out of our New York City, Austin, Seattle or San Francisco offices, or work fully remotely on standard East Coast business hours.

Responsibilities:

• Design and build core security primitives and services that protect MongoDB Atlas compute, networking, and identity across AWS, Azure, and GCP
• Build secure-by-default infrastructure using Linux security mechanisms (AppArmor, SELinux, seccomp, cgroups), Kubernetes, and eBPF to enforce runtime policies and gain deep visibility into systems behaviour
• Develop APIs, automation, and tooling that manage security posture at scale (CSPM, vulnerability management, workload identity) and provide monitoring, logging, and alerting pipelines that integrate with our tooling (Grafana, Splunk, Victoria Metrics.)
• Integrate security into our CI/CD and infrastructure-as-code workflows (Terraform) so that security controls are versioned, reviewed, and deployed just like any other code
• Lead complex projects end‑to‑end, from problem discovery and design docs to implementation, rollout, and long‑term ownership
• Collaborate with SRE, platform and product engineering teams to define secure architectures for new infrastructure and services

Qualifications:

You might be a great fit if you match some of the following:

• 5+ years of experience in Software Engineering, Site Reliability Engineering, or similar roles, preferably with relevant security work
• Proficiency with at least one programming language (Java, Golang, Rust, Python, or C/C++) and experience with infrastructure-as-code tools (Terraform) to automate security configurations and processes
• A deep understanding of Linux and networking concepts, including low-level fundamentals, and how they work together in complex systems
• Experience building security-related features or platforms such as runtime monitoring, CSPM, or vulnerability management
• Experience with a cloud provider (AWS, GCP, or Azure) and their security best practices and building blocks
• Hands-on experience with Kubernetes and its security ecosystem (e.g. RBAC, OPA/Gatekeeper, Kyverno, eBPF, Falco, Tetragon)
• A systems mindset: you think about failure modes, performance, observability, and operability alongside security and correctness
• Strong communication skills and the ability to explain complex security concepts and tradeoffs to both technical and non-technical stakeholders

About MongoDB

MongoDB is built for change, empowering our customers and our people to innovate at the speed of the market. We have redefined the database for the AI era, enabling innovators to create, transform, and disrupt industries with software. MongoDB’s unified database platform—the most widely available, globally distributed database on the market—helps organizations modernize legacy workloads, embrace innovation, and unleash AI. Our cloud-native platform, MongoDB Atlas, is the only globally distributed, multi-cloud database and is available across AWS, Google Cloud, and Microsoft Azure.

With offices worldwide and nearly 60,000 customers—including 75% of the Fortune 100 and AI-native startups—relying on MongoDB for their most important applications, we’re powering the next era of software.

Our compass at MongoDB is our Leadership Commitment, guiding how and why we make decisions, show up for each other, and win. It’s what makes us MongoDB. 

To drive the personal growth and business impact of our employees, we’re committed to developing a supportive and enriching culture for everyone. From employee affinity groups, to fertility assistance and a generous parental leave policy, we value our employees’ wellbeing and want to support them along every step of their professional and personal journeys. Learn more about what it’s like to work at MongoDB, and help us make an impact on the world!

MongoDB is committed to providing any necessary accommodations for individuals with disabilities within our application and interview process. To request an accommodation due to a disability, please inform your recruiter.

MongoDB, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type and makes all hiring decisions without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.

Req ID: 2263171228

At Natera, we revolutionize medicine by developing genetic products that combine cutting-edge technology and science. Our mission is to accelerate breakthroughs in research and improve patient care.

We are seeking a high-efficiency, adaptable, Java-centric AI Full-Cycle Engineer. The ideal candidate will have experience developing medium-to-high complexity products and providing critical production support. 

PRIMARY RESPONSIBILITIES:

• Perform system analysis, assess risks, develop technical design and implementation strategies, deliver high quality software. 

• Have a holistic view of processes and systems involved in taking patient samples from order to result in a multi-product clinical laboratory.

• Debug and perform root cause analysis for product defects and issues, as well as production support, while improving system observability and monitoring to prevent future regressions.

• Create and maintain comprehensive software documentation (software specification, test protocols and results, etc).

• Collaborate with the team on solutioning, knowledge share and efficient delivery.

• Drive adaptiablity via AI and leverage agentic AI to build adapters that power automation.

• This role regularly involves Protected Health Information (PHI). You must complete all required HIPAA/PHI privacy and security training within the first 30 days of hire and maintain current status on all Natera training requirements.

QUALIFICATIONS:

• Minimum of 10 years of experience in both server-side (back-end) and front-end development for complex n-tier systems, with at least 4 years focused on complex systems and integrations.

• Back-end: Minimum of 5 years of recent, hands-on experience with Java, preferably using open-source frameworks such as Spring.

• Front-end: Recent hands on experience with front-end development.

• APIs: Recent hands-on experience working with and developing REST APIs.

• Database: Extensive working knowledge of relational databases, experience using frameworks like Hibernate/JPA.

• Quality: Recent hands on experience with test design and automation.

• The "AI Glue": Experience using AI tools (e.g. Claude Code) not just for boilerplate, but for accelerating the mapping of complex data structures between systems.

• Adaptability: Proven track record of pivoting between tech stacks based on business needs (e.g., bridging modern AI agents with legacy JSP/Java architectures).

• BS degree in Computer Science or equivalent work experience.

KNOWLEDGE, SKILLS, AND ABILITIES:

• A solution- and continuous-improvement-oriented mindset with proactivity in troubleshooting.

• Strong communication skills.

• Willingness and ability to rapidly learn new practices, languages, and subject matter.

• Excellent understanding of core software engineering principles: Object-Oriented Programming (OOP), SOLID, etc.

• Experience with containers (e.g., Docker, Kubernetes).

• Experience working with various AI tools (e.g. Claude Code)

• Experience with distributed version control systems (e.g., Gitlab) and familiarity with branching strategies.

• Experience with message brokers/queues (e.g., Apache Kafka, AWS SQS) is a plus.

• Experience with JSP and JavaScript is preferred.

• Familiarity with software life cycle management tools (e.g., Jira).

• Ability to work effectively with people across multiple time zones.

• Experience developing software in a regulated environment is a plus.

#LI-DNI

JOB SUMMARY 

We are seeking a Staff Simulation Engineer to be the sole owner of dexterous hand simulation at Apptronik.

This is a high-autonomy, high-impact individual contributor role. You will define how hands are represented in simulation — from contact geometry and physics fidelity all the way through sim-to-real validation — and you will be the authoritative technical voice across Mechanical Design, Controls, and Hardware whenever simulation of the hand is in scope. There is no team beneath you, but your work directly unblocks multiple teams.

Core mandate: make simulation a reliable predictor of physical hand behavior, and own that standard end-to-end.

ESSENTIAL DUTIES AND RESPONSIBILITIES

Contact Dynamics & Physics Fidelity: Own the accuracy of contact simulation for high-DOF robotic hands. Model and tune contact parameters — stiffness, damping, friction, restitution — against real hardware measurements. Develop and maintain hand-specific collision geometry (primitive decomposition, mesh optimization) to ensure simulation contact behavior matches physical interaction.

Sim-to-Real Validation: Design and execute systematic sim-to-real validation workflows. Run side-by-side comparisons of grasping stability, fingertip contact forces, and joint behavior between simulation and hardware. Drive iterative parameter calibration using real sensor data — encoders, F/T sensors, tactile arrays — until simulation predictions are quantifiably reliable

Sensor & Actuator Modeling: Build accurate models of the hand's sensing and actuation systems within simulation — including tactile sensor response, actuator dynamics (compliance, backlash), and encoder noise characteristics.

Evaluation Scene Construction: Design and implement evaluation environments and dexterity benchmarks in Isaac Lab / Isaac Sim. Own the physical property modeling — contact materials, object mass/inertia, surface textures — required for high-fidelity task simulation.

Asset Pipeline: Contribute to CAD-to-USD conversion workflows as needed — collision mesh generation, joint limit extraction, kinematic parameter import. This is infrastructure support, not a primary focus.

SKILLS AND REQUIREMENTS

Must-Have

• 4+ years of hands-on robotic simulation experience (Senior); 7+ years (Staff)
• Experience with robotic hands or high-DOF manipulators
• Demonstrated experience with contact-rich simulation — not just kinematics and trajectory playback
• Experience with physics parameter identification (sysid) or domain randomization pipelines
• Proven ability to operate as a domain owner: setting technical direction, making independent architectural decisions, and driving cross-functional alignment through expertise
• Strong Python skills; C++ a plus
• Solid fundamentals: rigid body dynamics, contact mechanics, collision geometry, spatial math
• Hardware-grounded: experience running sim-to-real comparisons with real sensor data

Nice-to-Have

• Deep working knowledge of Isaac Sim, MuJoCo, or equivalent modern robotics simulator
• Familiarity with tactile sensing or F/T sensor integration in simulation
• USD proficiency: composition arcs, layers, stages
• Background in teleoperation or motion retargeting

EDUCATION and/or EXPERIENCE 

• MS or PhD in Robotics, Computer Science, Mechanical Engineering, or related fields.

PHYSICAL REQUIREMENTS 

Prolonged periods of sitting at a desk and working on a computer
Must be able to lift 15 pounds at times
Vision to read printed materials and a computer screen
Hearing and speech to communicate

Staff Bring-Up and Characterisation Engineer

Salary $191,100 - $258,500 + Phantom Equity + Benefits

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing.  

We are looking for a Characterisation and Bring-Up engineer to work with Architecture, Silicon Engineering, Hardware Engineering, Operations (device manufacture) and Product teams to help create and execute the bring-up and characterisation of our cutting-edge silicon devices and system platforms.
Graphcore design and develop leading edge silicon processors and high-power high-speed blade systems at the forefront of AI technology. As such you will need to develop a detailed understanding of our silicon and platform products. Your role will be to create and execute bring-up and characterisation plans of our silicon devices in systems to show that they will operate correctly over all conditions in the final product. You will concentrate on automated and manual testing of systems in the lab and datacentre. The results will be integrated with data from other teams to provide the complete characterisation solution for the product. For example, a large amount of device testing can be performed by the production test team using high-speed production test equipment. 

Responsibilities and Duties 

• Understand the architecture and design of silicon devices and systems, and clearly document the requirements for characterisation
• Creation of product specific characterisation plans
• Liasing with engineering teams to understand what are tests are available for characterisation purposes and driving change where appropriate
• Create and maintain an automated system for running characterisation testing, capturing the results to a central database and performing data analysis
• Execution of manual characterisation tests where automation is not appropriate
• Report regularly on progress and issues during the characterisation
• Produce characterisation reports containing platform test results and feeding them up into the overall product characterisation report

Essential skills

• A proven track record of delivering technical output, perhaps as an individual contributor, manager, or project manager
• Solid experience and understanding of silicon digital device design characterisation
• Knowledge of silicon process technology and how that impacts device performance at transistor and system level
• Knowledge of high-performance processor and system-on-chip systems
• Experience of high-speed digital interfaces, such as PCIe, Ethernet or DDR
• Knowledge of measurement automation and data analysis
• The ability to code or script automation and data analysis using appropriate coding languages such as Python, JMP for example
• An ability to work independently without daily oversight

Desirable skills:

• Knowledge of PCBA and system level technologies
• Background knowledge of ATE systems and capabilities. Whilst you will not be directly involved with such testing, some of the characterisation work will be performed on such systems

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Staff Bring-Up and Characterisation Engineer

Salary $198,100 - $268,000 + Phantom Equity + Benefits

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing.  

We are looking for a Characterisation and Bring-Up engineer to work with Architecture, Silicon Engineering, Hardware Engineering, Operations (device manufacture) and Product teams to help create and execute the bring-up and characterisation of our cutting-edge silicon devices and system platforms.
Graphcore design and develop leading edge silicon processors and high-power high-speed blade systems at the forefront of AI technology. As such you will need to develop a detailed understanding of our silicon and platform products. Your role will be to create and execute bring-up and characterisation plans of our silicon devices in systems to show that they will operate correctly over all conditions in the final product. You will concentrate on automated and manual testing of systems in the lab and datacentre. The results will be integrated with data from other teams to provide the complete characterisation solution for the product. For example, a large amount of device testing can be performed by the production test team using high-speed production test equipment. 

Responsibilities and Duties 

• Understand the architecture and design of silicon devices and systems, and clearly document the requirements for characterisation
• Creation of product specific characterisation plans
• Liasing with engineering teams to understand what are tests are available for characterisation purposes and driving change where appropriate
• Create and maintain an automated system for running characterisation testing, capturing the results to a central database and performing data analysis
• Execution of manual characterisation tests where automation is not appropriate
• Report regularly on progress and issues during the characterisation
• Produce characterisation reports containing platform test results and feeding them up into the overall product characterisation report

Essential skills

• A proven track record of delivering technical output, perhaps as an individual contributor, manager, or project manager
• Solid experience and understanding of silicon digital device design characterisation
• Knowledge of silicon process technology and how that impacts device performance at transistor and system level
• Knowledge of high-performance processor and system-on-chip systems
• Experience of high-speed digital interfaces, such as PCIe, Ethernet or DDR
• Knowledge of measurement automation and data analysis
• The ability to code or script automation and data analysis using appropriate coding languages such as Python, JMP for example
• An ability to work independently without daily oversight

Desirable skills:

• Knowledge of PCBA and system level technologies
• Background knowledge of ATE systems and capabilities. Whilst you will not be directly involved with such testing, some of the characterisation work will be performed on such systems

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute.

It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of a best-in-class family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.

Graphcore’s teams are drawn from a diverse set of backgrounds and bring a broad range of skills and perspectives.   A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.

Job Summary

We are seeking a principled and dynamic Lead Systems and Validation Engineer to drive end-to-end system validation for AI compute blade and rack platforms. This high-visibility role focuses on first silicon bring-up, system enablement, and post-silicon validation across hardware, firmware, and software domains. You will lead validation strategy, execution, and debug while collaborating closely with cross-functional engineering teams to deliver high-quality, industry-leading AI systems.

The Team

The Systems Validation team is responsible for enabling and validating Graphcore’s AI compute platforms from first silicon through production. The team works closely with system architects, firmware, silicon, and infrastructure teams to ensure system readiness, scalability, and quality at rack level.

Responsibilities and Duties

• Lead system enablement including first silicon bring-up and integration of firmware and platform components to meet system architecture specifications.
• Develop validation methodologies, lab hardware infrastructure, system software capabilities, and debug tools for blade and rack-level validation.
• Triage and debug issues across bring-up, post-silicon validation, and production phases ensuring timely resolution with high quality.
• Define and own validation test plans, develop test cases, and drive execution across domains such as CPU, GPU, memory, HBM, and IO.
• Drive innovation in validation through development of tools, scripts, and improved methodologies to enhance coverage, efficiency, and quality.
• Enable comprehensive system verification by integrating storage, networking, and infrastructure capabilities within lab environments.  
• Collaborate with multi-functional teams including system architecture, embedded software, hardware build, and ODM partners.    
• Provide technical leadership and mentorship, fostering engineering perfection and continuous improvement.

Candidate Profile

Essential:

• Strong analytical and problem-solving skills with high attention to detail.
• Extensive experience in system validation encompassing initial silicon integration and HW/FW/SW validation.  
• Strong understanding of industry-standard interfaces such as PCIe and CXL.
• Experience enabling storage and networking systems in lab environments for end-to-end validation.
• Deep knowledge of ARM or x86 architectures, SoC design, memory, RAS, and power management.
• Experience with system-level debug, operating systems, BIOS, and device drivers.
• Strong experience with Linux, Windows, and virtualization technologies (VMware, KVM, Hyper-V).
• Excellent communication, organization, and cross-functional collaboration skills.
• Ability to lead multiple workstreams and deliver under tight timelines.
• Experience in technical program management and driving validation initiatives.

Desirable:

• Master’s or PhD in Electrical Engineering, Computer Engineering, or related field.
• Demonstrated ability working on complex system validation and debug in data center or rack-scale environments.
• Experience designing or validating AI/ML rack-scale systems.
• Knowledge of hardware development best practices and industry standards.
• Familiarity with emerging AI and data center infrastructure technologies.
• Experience collaborating with ODM partners globally.

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute.

It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of a best-in-class family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.

Graphcore’s teams are drawn from a diverse group of backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.

Job Summary

We are seeking a senior validation lead engineer to lead at-scale rack validation efforts for next-generation AI hyperscale systems. This role focuses on post-silicon system validation across the full lifecycle, ensuring functional, electrical, and thermal performance meets product objectives. You will own end-to-end blade and rack validation including planning, development, execution, and debug while collaborating across firmware, systems, and hardware teams.

The Team

The Rack Validation team is responsible for ensuring system readiness and quality at scale. The team works cross-functionally with firmware, silicon, and system engineering teams to validate complex AI compute platforms.

Responsibilities and Duties

• Lead post-silicon validation of AI compute blades and racks including test planning, development, and automation.
• Drive provisioning and integration of system components (SoC FW, BMC, RMC, OS) for rack-level readiness.
• Own execution against program achievements and report validation progress and risks.
• Triage test failures, collect debug data, and collaborate on root cause analysis.
• Track validation coverage and continuously improve test processes and infrastructure.
• Collaborate with ODM/JDM partners on validation and quality.
• Mentor engineers and drive engineering excellence.

Candidate Profile

Essential:

• Bachelor’s or Master’s degree or equivalent experience in Computer Engineering, Electrical Engineering, Computer Science, or related field.
• Proven track record in system, rack, or embedded validation with leadership experience.
• Strong experience in large-scale hardware validation environments.
• Expertise in CPU/GPU, memory, IO, and firmware validation.
• Experience with Linux/server OS and automation using Python/Bash.
• Knowledge of IPMI, Redfish, PLDM.
• Experience with CI/CD pipelines and hardware interfaces.

Desirable:

• Experience in hyperscale environments.
• Familiarity with OpenBMC and processes for verifying firmware functionality.  
• Knowledge of firmware security and HIL testing.
• Experience with test management tools.

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute.
It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.

Job Summary

Graphcore is seeking a Staff Mechanical Engineer to join our Data Center Engineering organization and drive engineering coordination efforts with external data center developers. You will be working with a multi-disciplinary team of technical leaders to deliver best-in-class infrastructure solutions. The ideal location for this position will be based out of Austin. Roughly 10-20% travel time can be expected..

The Team

The Data Center Engineering team is responsible for the design, development, and deployment of infrastructure that supports Graphcore’s advanced AI compute platforms.
The team collaborates with internal engineering groups, external consultants, and data center developers to deliver reliable and scalable environments for high-performance computing workloads.

Team members work across multiple disciplines—including mechanical, electrical, facilities, and IT infrastructure—to ensure that Graphcore’s data center deployments meet stringent performance, efficiency, and operational reliability requirements.

Responsibilities and Duties

• Develop and review design standards and specifications, ensuring alignment with industry standard methodologies and Graphcore’s reliability goals.
• Perform detailed engineering analysis of designs, ensuring efficiency and reliability of operation.
• Provide direction, coordinate with, and review the designs of external consultants and partners.
• Ensure delivery of future-proof engineered solutions.
• Conduct site inspections and attend factory visits critical infrastructure and equipment.
• Define and issue owner’s requirements for mechanical systems design.
• Manage design teams from an owner’s perspective and make decisions to keep projects moving forward.
• Stay informed on the latest industry developments and emergent technologies within the data center industry.

Candidate Profile:

Essential:

• Bachelor’s degree or equivalent experience in Mechanical Engineering or related field.
• Deep technical knowledge of HVAC equipment and systems including: chillers, boilers, pumps, air handling equipment, duct and piping design, sequence of controls.
• Experience coordinating with IT teams for infrastructure design in support of HPC racks and data centers.
• Excellent interpersonal skills and ability to collaborate in a cross-discipline team.
• Comfortable with a fast-paced environment that is rapidly developing and changing.
• Professional Engineering (PE) license or equivalent international certification (this position will not be stamping drawings as EOR).

Desirable:

• Prior experience with hyperscale data center environments or co-location facilities at the Tier III or Tier IV levels as defined by Uptime Institute.
• Experience with plumbing systems equipment and design (domestic water, waste/vent, etc.)
• Visio, BlueBeam, AutoCAD, Revit, or other design and drafting software.

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.

Job Summary

We are seeking a Staff Hardware Engineer to provide advanced operational, diagnostic, and engineering support for Graphcore’s Arm-based hardware platforms across lab and data center environments.

This role focuses on supporting hardware bring-up, validation, and troubleshooting of complex AI compute platforms, including server blades, racks, and rack-scale infrastructure. The successful candidate will collaborate closely with engineering, platform, and data center teams to ensure the reliability and performance of next-generation AI systems.

The Team

The Systems Engineering and Hardware Engineering teams are responsible for enabling the bring-up, validation, and operational reliability of Graphcore’s AI infrastructure platforms.

The team works closely with server engineering, firmware teams, platform architects, and data center operations to support the development, testing, and deployment of next-generation AI compute systems.

This collaborative environment enables rapid problem-solving and continuous improvement of Graphcore’s hardware platforms from early development through production deployment.

Responsibilities and Duties

• Lead advanced break-fix troubleshooting for server blades, motherboards, power systems, and rack-scale infrastructure.
• Support engineering bring-up activities, including component validation and firmware interaction testing.
• Diagnose system-level failures involving thermal behavior, power anomalies, network configuration, and BIOS/BMC issues.
• Collaborate with server engineering teams to perform root cause analysis and propose corrective actions or design improvements.
• Support deployment and rollout of next-generation hardware platforms through structured validation and qualification cycles.
• Interface with facilities and infrastructure teams to understand environmental factors impacting system reliability.
• Develop and maintain standard operating procedures (SOPs), troubleshooting guides, and validation documentation.
• Provide guidance and mentorship to junior technicians and engineers on troubleshooting methodologies and hardware diagnostics.
• Participate in on-call rotations or off-hours support during critical engineering milestones or hardware bring-up phases.

Candidate Profile

Essential

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
• Strong experience with server hardware architectures and board-level debugging.
• Experience analyzing system logs, hardware telemetry, and power/thermal metrics to isolate hardware failures.
• Hands-on experience with HPC systems, AI compute platforms, or rack-scale infrastructure.
• Strong collaboration skills and ability to work effectively in fast-paced engineering environments.
• Excellent written and verbal communication skills.

Desirable

• Experience supporting prototype or pre-production hardware bring-up.
• Familiarity with data center facilities, including liquid cooling and power distribution systems.
• Experience using Python, Bash, or automation tools for hardware validation or troubleshooting.
• Exposure to structured failure analysis and reliability engineering methodologies.

Staff Systems Design Engineer (Hybrid - 2 to 3 days onsite per week) 

Overview:

Lead the evolution of Weedmaps' design system through an incredible period of opportunity. We’re looking for a transformative and visionary designer, with exceptional taste and craft, to collaborate in leading efforts to modernize the Weedmaps customer experience. 

This role unifies design and code at the intersection of Design, Engineering, and AI tooling, to evolve, operationalize, and scale the system while modernizing it and transforming it. Our goal is that this work will continually accelerate design and development, maintain high standards for craft and usability, align with engineering architecture, and enable consistent app-wide changes. Success will require a highly collaborative individual, eager to partner with Creative (new brand shifts, cohesion, continual evolution), Product Design (new feature development, iteration) and Engineering (CI/CD, tokens, tooling), to ensure system adoption and power the product experience.

The impact you'll make:

• Define and evolve the multi-platform system (web + mobile) with clear architecture, governance, and scalability principles.
• Own the roadmap and prioritization based on product needs, adoption gaps, and system performance.
• Partner with Design and Creative leadership to ensure high craft, modern interaction patterns, and resilience to ongoing brand evolution.
• Design and implement core system components, defining intuitive, flexible, and scalable APIs, variants, and composition patterns.
• Ensure high standards for visual precision, fidelity, accessibility (React Aria), and interaction quality, motion, and state management.
• Continuously refine components based on product usage and edge cases.
• Implement automated quality systems, including visual regression testing, and continuously audit the system for usability and craft excellence. Act as a cross-functional steward of system quality.
• Lead migration of legacy UI and ensure critical product surfaces (e.g., CTAs, checkout flows) are powered by the system, actively increasing adoption across the ecosystem.
• Establish a best-in-class tool-to-code pipeline (Figma, Claude, Builder, etc.) to map design artifacts to production components and prevent drift.
• Partner with Engineering on architectural decisions (CI/CD, token systems, distribution infrastructure) and support enforcement mechanisms (linting, token constraints) to maintain system integrity.
• Introduce and standardize AI-assisted workflows, in partnership with Engineering , to structuring components for AI-friendly generation and integrating tools (Builder.io, Claude, etc.) to improve consistency.
• Mentor designers and engineers and create documentation that allows teams to move quickly within a well-governed system.
• Identify strategic innovation opportunities, prototype new interaction models/motion systems, and codify successful innovations into the design system.

What you've accomplished:

• 7+ years in front-end, design, or creative engineering, with strong mobile focus (iOS/Android).
• Proven track record building and scaling design systems and component libraries across multiple teams/products.
• Knowledge of React (Web) and React Native, and modern front-end architecture.
• Deep understanding of design craft (typography, motion, interaction, visual systems).
• Experience driving adoption of shared systems and implementing design-to-code pipelines (tokens, Figma integration).
• Familiarity with AI-assisted development tools and workflows.
• Strong systems thinking and ability to align Design, Engineering, and Creative stakeholders.

Bonus points: 

• Experience working on marketplace, e-commerce, or consumer platforms.
• Familiarity with Storybook, visual regression tools, and token management systems.
• Experience translating brand systems into scalable product UI.
• Exposure to AI-native development environments and workflows.
• Passion for building systems that balance craft, scalability, and speed.

What Success Looks Like:

• Achieve measurable increase in system adoption and reduction in custom UI, ensuring core experiences (e.g., CTAs, checkout) are powered by shared components.
• Enable teams to ship UI faster and with higher consistency.
• Maintain tight alignment between Design and code, minimizing drift.
• Seamlessly translate brand updates into product through the system.
• Establish efficient AI-assisted workflows for both Design and Engineering.
• The product delivers a cohesive, modern, and high-quality user experience.

Why You’ll Love It Here:

• Shape product development at scale, operating at the center of Design, Engineering, and Creative.
• Work with modern infrastructure to define how AI, design systems, and product development converge.
• Build systems that power millions of user experiences.
• Thrive in a culture that values craft, collaboration, and innovation.

The base pay range for this position is $186,251 - $208,959 per year

 2026 US Benefits for Full Time, Regular Employees:

• Physical Health (Medical, Dental & Vision)
• 100% employer-paid premium for employees
• Up to 80% coverage for dependents
• Company HSA contribution with the High Deductible Health Plan
• 401(k) Retirement Plan (employer will match contribution up to 3.5% of employee contribution)
• Basic Life, Voluntary Life and AD&D Insurance options
• Supplemental, voluntary benefits
• Student Loan Repayment/529 Education Savings with a monthly company contribution
• FSA (Medical, Dependent, Transit and Parking)
• Voluntary Life and AD&D Insurance
• Critical Illness Insurance
• Accident Insurance
• Short- and Long-term Disability Insurance
• Pet Insurance
• Identity theft protection
• Legal access to a network of attorneys
• PTO, paid sick leave, and company holidays (including a 2026 holiday shutdown)
• Paid parental leave

At Qualia, we've built the leading B2B real estate technology that transforms the home buying and selling experience into a simple, secure, and enjoyable process. Our SMB and Enterprise products bring together users from across the real estate ecosystem---homebuyers and sellers, lenders, title and escrow agents, and real estate agents---onto a single shared digital closing platform, providing greater clarity and transparency to real estate transactions. Today, through our business customers across the country, millions of consumers use Qualia to close on homes every year.

WHAT YOU'LL WORK ON

We're hiring a Senior Application Security Engineer to join a small, high-leverage AppSec team. This is a deep-technical IC role with a staff-leaning scope: you'll set the technical direction and own delivery on how we find, fix, and prevent vulnerabilities across Qualia's products and cloud infrastructure, and you'll be the person other engineers want in the room when an architecture decision has a security dimension.

You'll partner daily with product engineering, infrastructure, and platform teams, and you'll work closely alongside our existing AppSec engineers - raising the technical bar of the team while staying deeply hands-on with code, tooling, and adversarial testing. This is the right role for someone who is as comfortable writing a Burp extension or a Semgrep rule as they are pairing with a product engineer to land a fix.

RESPONSIBILITIES

• Run offensive assessments against Qualia's applications and infrastructure: manual penetration testing, exploit development, authenticated web/API testing, and adversarial review of new designs before they ship
• Lead threat modeling and secure design review for the highest-risk initiatives across the company, and mentor engineers to do the same for their own work
• Own and evolve our AppSec tooling stack end-to-end - SAST, DAST, SCA, secret scanning, IaC scanning, and the CI/CD gates that tie them together. Build the custom rules, detections, and automation that generic tooling doesn't give us
• Harden our cloud posture: review AWS configurations, IAM policies, Kubernetes/EKS workloads, and networking boundaries; build automation and guardrails that prevent the same class of issue from recurring
• Reduce toil for the team - write the tools, scripts, and integrations that turn a day of triage into a few minutes
• Partner with Infrastructure and Platform on detection engineering, incident response support, and cross-cutting programs (secrets management, supply chain, runtime security)
• Set the technical bar for the AppSec team: raise the quality of reviews, establish patterns others can reuse, and mentor peers across seniority levels
• Represent AppSec in architectural reviews, vendor evaluations, and compliance efforts

YOUR BACKGROUND THAT LIKELY MAKES YOU A MATCH

• 8+ years of hands-on experience in application security, offensive security, or security engineering, with demonstrable depth in at least two of: offensive testing, security tooling/automation, and cloud/infra security
• Strong offensive skills - you can manually exploit real web and API vulnerabilities beyond what a scanner will find, and you can teach others to do the same
• Deep familiarity with building and operating security tooling in a modern engineering org: SAST/DAST/SCA pipelines, custom detection rules, secrets scanning, and CI/CD security gates. You've written tooling, not just configured it
• Production experience with AWS (IAM, VPC, networking, data services), containerized workloads (Docker, Kubernetes/EKS), and infrastructure-as-code (Terraform or similar)
• Comfort reading, reviewing, and contributing code in at least one language common to modern web stacks (Python, Go, Ruby, TypeScript, or similar)
• Clear, direct communication style. You can make a sharp technical argument to senior engineers, translate risk into business terms for leadership, and write a bug report an engineer actually wants to fix
• Strong partnership instincts - you get leverage by making other teams faster, not by blocking them

NICE TO HAVE

• Experience in fintech, proptech, healthcare, or another regulated industry where data sensitivity is high
• Background meaningfully contributing to a bug bounty program
• Experience with identity and access systems (OIDC, SAML, federation, fine-grained authorization)
• Detection engineering, DFIR, or red-team experience
• Open source contributions to security tooling, published research, or CVE credits
• Relevant certifications (OSCP, OSWE, GWAPT, GPEN, etc.) - valued but not required

While this role is remote work eligible, we have three office locations: San Francisco, California; Concord, New Hampshire; and Austin, Texas.

This role has a base annual salary of $180,000-$210,000  plus a competitive equity and benefits package. (Salary to be determined by relevant experience, location, knowledge, and skills of the applicant, internal equity, and alignment with market data.)

WHY QUALIA

Qualia is made up of incredibly bright, mission-driven coworkers who are passionate about using technology to solve real-world problems---and we're growing quickly. In order to continue building an engaging and dynamic organization, we're committed to giving everyone the support they need to do great work.

Our benefits package is designed to allow our team members to be their best selves, both in and out of the workplace. In addition to comprehensive health plans, a 401k program, and commuter benefits, we prioritize family and personal well-being through professional development, parental leave, and a flexible time off policy. Qualia offers a robust online onboarding program to train new hires, biweekly all hands meetings, and a variety of internal virtual events to keep employees connected.

We believe diverse perspectives and backgrounds are critical to building great technology, and our goal is to cultivate an environment where people feel equally valued and respected. Qualia is proud to be an equal-opportunity workplace, and we welcome applicants from all backgrounds regardless of race, color, ancestry, religion, gender identity or expression, sexual orientation, marital status, age, citizenship, socioeconomic status, disability, or veteran status.

By submitting your application, you acknowledge and agree to the collection, processing, and use of your personal information as described in our Employee Data Privacy Notice.

#LI-Remote

We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.

This role is hybrid, based out of Bengaluru, India.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced micro-architect who thrives in building CPU systems (multiple cores, multiple clusters of cores and subsystem components) from scratch.
• Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
• Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

What We Need

• 10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
• Collaborate closely with DV, PD, architecture and performance engineers to meet functional, timing, and power goals.
• Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
• Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
• Enhance RTL design environment, tools, and methodologies to improve development efficiency.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• How to design and optimize a custom RISC-V CPU system from first principles.
• Integration of open-source and industry-standard tools to improve RTL flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.

This role is hybrid, based out of Austin, TX, Fort Collins, CO or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced micro-architect who thrives in building CPU systems (multiple cores, multiple clusters of cores and subsystem components) from scratch.
• Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
• Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

What We Need

• 10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
• Collaborate closely with DV, PD, architecture and performance engineers to meet functional, timing, and power goals.
• Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
• Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
• Enhance RTL design environment, tools, and methodologies to improve development efficiency.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• How to design and optimize a custom RISC-V CPU system from first principles.
• Integration of open-source and industry-standard tools to improve RTL flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Santa Clara, CA or Austin, TX

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a BS/MS/PhD in EE/ECE/CE/CS with 5+ years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs.
• You are fluent in Verilog RTL for DFT logic (lock-up latches, clock gates, scan anchors) and comfortable with SystemVerilog/UVM.
• You have hands-on experience with ATPG and DFx insertion tools, fault models (Stuck-at, Transition, Path Delay, IDDQ, Cell-Aware), and low-power design flows.
• You bring strong debug and problem-solving skills across design hierarchies and collaborate effectively with design, PD, verification, and test teams.

What We Need

• Implement and integrate DFT features (scan, JTAG, compression, ASST, MBIST) into RTL from early design through tapeout across multiple IPs.
• Own ATPG, test coverage analysis, and gate-level simulation (e.g., with Synopsys VCS/Verdi) to achieve and maintain high-quality test coverage.
• Plan, implement, and verify MBIST, and work closely with Test Engineering on test planning, pattern delivery, and debug.
• Develop and refine DFx flows and methodology that integrate cleanly with front-end and physical design flows, balancing coverage, test cost, and design intrusiveness.

What You Will Learn

• How to drive DFT for industry-leading AI/ML architectures, working on high-performance chips with aggressive performance and power targets.
• Practical strategies to reduce test cost while maintaining coverage, and to design DFT hooks that accelerate silicon bring-up and yield learning.
• How to minimize DFT intrusions while integrating cleanly with RTL, verification, physical design, and production test flows.
• How a senior, cross-functional ASIC team collaborates across design, PD, verification, and manufacturing to achieve first-pass silicon success on advanced nodes.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Staff Design for Test STA Engineer at Tenstorrent, you will be a key technical leader in ensuring the testability, quality, and performance of our next-generation AI processors. This role requires a good understanding of both Design for Test (DFT) architecture and implementation, as well as comprehensive expertise in Static Timing Analysis (STA) for complex SoCs. You will be responsible for defining and implementing the full DFT methodology for our high-speed, multi-core designs, owning the top-level timing constraints and sign-off for all DFT modes, and collaborating closely with RTL, Physical Design, and Product Engineering teams to achieve first-pass silicon success.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Deep knowledge of core DFT concepts including Scan Compression and insertion, Memory BIST and repair schemes, JTAG/IJTAG, and at-speed test methodologies.
• Comprehensive understanding of Clock Domain Crossings (CDC), Reset Domain Crossings (RDC), timing sign-off modes and constraints, and proficiency in using industry-leading Static Timing Analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus etc).
• Deep knowledge of DFT specific timing modes including JTAG, Scan Shift, Scan Slow Capture, Scan Fast Capture, Memory BIST etc.
• Experience in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification.

What We Need

• Coordinate DFT requirements across SOC, IP and product teams and work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
• Lead the definition, generation, and validation of comprehensive DFT timing constraints (SDC) to ensure timing closure for all test modes (e.g., Scan, JTAG, Memory BIST).
• Own the STA sign-off for DFT modes at both the block and top-level, including corners and operating conditions, using industry-standard tools (e.g., PrimeTime, Tempus etc).
• Work closely with the Physical Design team (Synthesis, P&R) to drive timing convergence, resolve complex timing violations, and generate necessary timing ECOs.
• Identify and implement improvements to existing DFT and STA flows, enhancing efficiency and robustness.
• Participate in ATE targeted test patterns, validation and silicon- debug
• Work closely with test and product engineering teams on silicon characterization and validation.

What You Will Learn

• Advanced Design for Test (DFT) methodologies for cutting-edge AI processor architectures, including comprehensive scan insertion, Memory BIST, and at-speed test strategies
• In-depth Static Timing Analysis (STA) techniques for complex multi-core SoCs, mastering industry-standard tools like PrimeTime and Tempus to ensure timing closure across diverse operational modes
• Sophisticated cross-functional collaboration skills, working seamlessly with RTL, Physical Design, and Product Engineering teams to drive first-pass silicon success
• Innovative problem-solving approaches for resolving complex timing violations and optimizing test flows in high-performance semiconductor design environments

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we build open, state of art compute for real workloads and real developers.

You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are 

• You bring 8+ years in CPU verification or closely related digital design.
• You know high‑performance out‑of‑order CPU microarchitecture in depth.
• You work comfortably with RTL, waveforms, logs, and complex debug scenarios.
• You communicate clearly across design, DV, emulation, and post‑silicon teams.

What We Need 

• Plan and drive functional verification for CPU core features and microarchitectural scenarios.
• Develop UVM, assembly, and C/C++ stimulus for ISA and microarchitectural coverage.
• Develop/debug C++ functional models of RISC-V extensions and un-core components such as APIC and IOMMU.
• Debug simulation and emulation regressions using waveforms, logs, and RTL understanding.
• Build and refine coverage models to track and close architectural and microarchitectural coverage.
• Improve core, cluster, and chip‑level testbenches and debug infrastructure.
• Support design bring‑up across simulation, emulation, and post‑silicon environments.
• Collaborate with design, test, and validation to deliver robust CPU cores and clusters.

What You Will Learn 

• How Tenstorrent designs and validates high‑performance RISC‑V CPU cores and clusters.
• Techniques for spanning pre‑silicon, emulation, and post‑silicon verification with shared stimulus.
• Ways to scale coverage, debug, and infrastructure across multiple CPU programs.
• How open hardware and software fit into Tenstorrent’s broader compute roadmap.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we are building open, state of art compute for AI and RISC‑V CPUs. You will lead the technical efforts and strategy around our existing emulation infrastructure for high‑performance CPUs that power these products. Your work will directly enable silicon bring‑up, validation, and customer‑ready systems.

This role is hybrid, based out of Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have strong background in CPU verification, emulation, and debug.
• You are fluent in Verilog and SystemVerilog for complex SoC designs.
• You are a technical leader who drives complex debug efforts, solves ambiguous technical problems, and mentors younger engineers.
• Experience with Zebu emulation platforms is a significant plus.
• You collaborate closely with design, verification, and vendors to move fast and unblock teams.

What We Need

• Lead the technical strategy and execution to scale and optimize existing emulation infrastructure on commercial and open‑source platforms.
• Enable the emulation infrastructure and workflow, including producing reliable emulation builds.
• Drive and lead complex cross-functional debug and root cause analysis efforts.
• Optimize emulation performance and regression flows with Design Verification teams and tool vendors.

What You Will Learn

• How to bring state of art AI and CPU architectures to life on emulation.
• How to design large‑scale emulation regressions that mirror real customer workloads.
• How to tune emulation performance across different vendors and hardware platforms.
• How open hardware and software come together across Tenstorrent’s full compute stack.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

We’re looking for a Physical Design Engineer – EMIR to join our silicon team. In this role, you’ll lead EM and IR-drop simulations to ensure robust power delivery, signal integrity, and long-term reliability for high-performance ICs. You’ll work with RTL, physical design, and analysis teams to implement power grid strategies that optimize performance, power, and area (PPA), particularly at advanced nodes like 7nm and below. You’ll also support EMIR sign-off and waiver methodologies across the chip hierarchy.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A physical design specialist with deep experience in EMIR analysis and signoff.
• Comfortable navigating advanced technology nodes and power integrity challenges.
• Proactive and detail-oriented, with a passion for pushing performance and reliability boundaries.
• Collaborative and effective across teams working on RTL, physical design, packaging, and reliability.

What We Need

• 7+ years of experience in physical design or signoff, with a focus on EMIR.
• Hands-on with RedHawk, Voltus, or equivalent industry-standard EMIR tools.
  Strong understanding of IR-drop mitigation, EM compliance, and power grid design.
• Proficiency with layout extraction flows, RC modeling, and metal density checks.
• Experience working in advanced nodes (7nm, 5nm, 3nm), and with scripting languages like TCL, Python, Perl, or Shell.
• Knowledge of floorplanning, bump/RDL design, and sign-off flows (DRC/LVS, timing closure).

What You Will Learn

• How to architect and analyze robust power delivery for Tenstorrent’s RISC-V CPUs and AI chips.
• How to integrate EMIR signoff into fast-paced, high-performance chip design cycles.
• Best practices for hierarchical analysis and EMIR methodology across pre- and post-layout flows.
• Cross-functional collaboration for optimizing PPA while meeting stringent reliability goals.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is looking for a Staff Product Development Engineer - ATE Content Developer, who will be focused on core content development for high-performance AI/ML silicon. They  will be responsible for developing production test programs on ATE test platforms, translating DFT/ATPG content into optimized ATE solutions, and implementing Streaming Scan Network (SSN) architectures for efficient test data delivery. High level challenges include reducing test cost while maintaining coverage targets, optimizing test time for chiplet and multi-die architectures, and enabling rapid yield learning through robust test methodologies. The work is done collaboratively with a group of highly experienced engineers across DFT, design, product, and manufacturing domains.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced semiconductor test engineer with 7 years and a BS/MS in EE/ECE/CE and a track record testing complex digital devices on advanced nodes.
• Hands-on with Advantest V93K and/or Teradyne UltraFlex+ platforms, comfortable owning production test programs end‑to‑end.
• Deeply familiar with DFT/ATPG flows and test architectures: scan chains, MBIST, compression, JTAG/IEEE 1149.1, and common fault models (stuck‑at, transition, path delay, cell‑aware).
• Proficient in C/C++ or Java, with strong scripting skills in Python, Perl, or TCL to automate flows, pattern handling, and data analysis.
• Skilled at debugging across ATE hardware, test programs, and silicon, and at using data to drive root‑cause analysis and yield improvement.

What We Need

• Develop and optimize production test programs on Advantest V93K using the SmarTest 8 environment, from bring‑up through high‑volume manufacturing.
• Translate ATPG patterns (STIL/WGL) into production‑ready test content, balancing test time, coverage, and cost for chiplet and multi‑die AI/ML devices.
• Implement and debug Streaming Scan Network (SSN) based content for high‑speed scan delivery, ensuring robust and scalable scan test infrastructure.
• Own test content for scan, BIST, and memory test structures, collaborating with DFT teams on pattern debug, fault diagnosis, and coverage improvement.
• Support silicon bring‑up and debug in the lab and at manufacturing sites, including correlation, corner characterization, and PVT studies.
• Build and maintain automation scripts and test methods that improve productivity, repeatability, and quality across the test lifecycle.
• Document test architectures, flows, and debug procedures so they can be scaled across products, sites, and engineering teams.

What You Will Learn

• How to test and scale cutting‑edge AI/ML silicon with chiplet and multi‑die architectures, including exposure to 2.5D/3D packaging and HBM integration.
• Deeper expertise in SSN architectures, high‑speed scan delivery, and next‑generation DFT/test methodologies for complex HPC/AI devices.
• How to drive end‑to‑end yield learning: from ATE data and STDF analytics through to design, DFT, and manufacturing process feedback.
• How a fast‑growing AI hardware startup coordinates DFT, design, product, and manufacturing to bring new silicon from first silicon to high‑volume production.
• Opportunities to influence test strategy, infrastructure, and automation roadmaps for future products and platforms as Tenstorrent’s portfolio scales.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

FPGAs and ASICs are critical pieces of our technology stack. We are looking for talented hardware developers to architect and design complex systems on a highly collaborative global team. In this role, you'll identify efficient ways to perform on-the-fly transformations of market data and implement models with complex data structures in RTL. Deep knowledge of SystemVerilog, FPGA internals and/or ASIC primitives, computer architecture, and vendor tool suites are essential to succeeding in this role. Expertise in networking protocols, CPU design, and/or machine learning accelerators is a big plus. No financial experience is necessary.

Responsibilities

• Collaborate with a cross-functional team to develop and deploy custom FPGA and/or ASIC solutions for a wide range of trading applications
• Investigate new technologies and tools
• Contribute to a nimble hardware development tech stack

Qualifications

• Ability to describe hardware designs at a high level, low level, or anywhere in between
• Brilliant design, optimization, debugging and problem solving skills
• Professional experience (2+ years) in RTL design for FPGA or ASIC
• Expert SystemVerilog development skills with a thorough understanding of the language 
• Expert on low level FPGA or ASIC architectures, with a deep understanding of what makes them "tick"
• Skilled in network communications, processing pipelines, and/or machine learning
• Working knowledge of Python and/or C++
• Comfortable in a Linux environment
• Strong verification experience
• Familiarity with AMD Vivado is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

The Research and Development (R&D) team at Hudson River Trading (HRT) builds and maintains the computers, networks, data storage, operating systems, and software that allow our trading strategies and research environment to operate worldwide 24/7. The Storage team within R&D manages hundreds of petabytes of storage to facilitate industry-leading AI/ML-based trading.

We are seeking an experienced Storage Engineer who enjoys being challenged, appreciates an open and collaborative organizational structure, and thrives in a fast-paced environment. In this role, you will manage our existing storage infrastructure and be responsible for the design, automation, and management of future storage solutions to support our large-scale research environment. This is an exciting opportunity to join a small team focused on HPC storage and help set the direction for storage solutions at HRT. You’ll have freedom to research, propose, and test new hardware and software to improve the performance and usability of our research environment.

Responsibilities

• Design, deploy and manage a variety of storage solutions
• Troubleshoot complex storage, OS, and networking issues
• Build tools to improve the performance and monitoring of storage clusters
• Research and experiment with new storage solutions

Qualifications

• Knowledge of distributed file systems used for large-scale cluster computing (Lustre, CephFS, GPFS, etc.) 
• Ability to design a home grown NAS storage solution with redundancy and high availability
• 3+ years of experience in HPC-like environments with large scale storage deployments greater than 1PB
• 3+ years of experience with scale-out enterprise storage solutions such as Isilon, VAST, NetApp, and Pure
• Extensive experience with Linux troubleshooting and NFS
• Strong knowledge of Linux, ZFS, and other Linux filesystems
• Proficient in Python and shell scripting 
• Strong cross-functional communication skills
• Ability to analyze and solve problems quickly in a fast-paced environment
• Exceptional time management skills and the ability to balance independent and collaborative workflows 
• Eager to learn and apply new skills

The estimated base salary range for this position is 150,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading’s High Performance Computing (HPC) Network Engineering team designs and engineers the low-latency communications infrastructure that underpins our incredibly large GPU and CPU compute clusters. Our mandate is to architect, optimize, and scale the high-performance LAN and WAN infrastructure that interconnects globally distributed, large-scale on-prem data centers, enabling them to grow rapidly and operate at peak performance in support of HRT’s demanding computational workloads. 

We are looking for a Network Engineer with deep experience in designing, deploying, and scaling networks for large-scale HPC environments. You will be building the next generation of infrastructure required by a premier algorithmic trading firm operating at the forefront of technology and finance.

This position requires deep technical skills, along with the  product leadership and vision needed for the future of cloud-scale networking. You’ll have broad responsibilities and freedom to analyze and solve problems, and your solutions will have an immediate impact on our operations worldwide. We’re looking for someone who loves  technology and is excited about tackling big picture problems. You will work on a wide variety of projects to enhance the performance and capacity of the network and contribute to both the management and the technical nitty-gritty of our computing architecture. Our people and our compute capabilities are our two most important differentiators, and that is where we are investing the most.

Responsibilities

• Network design, product selection, routing, configuration and troubleshooting
• Closely work with our HPC Systems team, as well as other teams to scale our research environment 
• Meet with external parties for project related items as well as future endeavors
• Overall capacity planning for the data center networks
• Develop scripts and processes to increase efficiency
• Collaborate with others in the network team to solve cross discipline problems
• Provide detailed documentation 
• Mentor others as a senior resource 

Profile

• 10+ years of relevant experience
• Proven ability to prioritize workloads and manage implementation schedules with a meticulous attention to detail 
• Proactive problem-solver with the technical skills and hands-on mentality to tackle challenges in the field.
• Strong collaboration skills and a focus on continuous improvement, with the humility to own and learn from mistakes 

Skills

• Excellent oral and written communication skills: able to distill complicated issues into clear and concise terms
• Able to create and maintain clear and effective technical documentation
• In depth understanding of common layer 2 and layer 3 network protocols (OSPF, BGP, PIM, IGMP, RoCEv2, spine-leaf architecture, and VXLAN) and best practices for them
• Proven ability to select and work with vendors to engineer switches for next-generation computing environments
• Experience managing Arista (EOS), Cisco (NX-OS), Nvidia (Cumulus) and SONiC-based switches, as well as an interest in exploring new platforms
• Strong design skills in computing and grid networks, with expertise in capacity planning, and full lifecycle project management
• Experience with packet decoding and analysis tools such as tcpdump and Wireshark
• Experience with public cloud networks, such as AWS, GCP, Azure
• Familiarity with configuration management tools, such as Ansible or Salt is desirable to support zero-touch network management
• Familiarity with Python, Prometheus, Grafana, ELK, GitHub is desirable
• Understanding of basic power consumption and cooling issues in a data center environment
• Knowledge of fiber optics technology and cabling standards ranging from 1 to 800 Gbps. Ability to sort through specs and make recommendations on appropriate purchases.
• Skilled in Unix/Linux command line utilities and networking stack
• Experience with AI style network designs and workloads is preferred

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. 

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

Hudson River Trading (HRT) is looking for a Junior Crypto Electronic Trading Support Engineer to join our Trade Operations (TradeOps) team in our London office. This team is responsible for managing HRT’s live trading environment, one of the most robust and efficient electronic trading platforms in the world. This includes configuring, monitoring, and optimizing the firm’s crypto trading as well as handling related risk, regulatory, and development tasks. The TradeOps team focuses on automating common tasks and preparing for the unexpected: your day could consist of debugging to get a process running in time for the market open, making a difficult on-the-spot decision that balances compliance, risk, and PnL during trading hours, or coordinating the technical rollout of a new trading strategy. 

Being a member of TradeOps at HRT supporting crypto means working on a tight-knit, highly productive team. We're looking for someone who loves technology, is passionate about crypto, and wants to work on a broad range of projects using whatever tools best solve the problem at hand. Excellent cross-functional communication skills are a must, along with a can-do attitude.

In a high-performance environment, immediate awareness of and reaction to systems and trading issues is essential. That’s where HRT’s Electronic Trading Support Engineers come in. You’ll be responsible for onboarding new crypto markets, managing new initiatives, and ensuring a smooth trading day. You will be the first line of defense when issues arise, and the subject matter expert on recent changes to the production trading platform. The TradeOps team’s scope covers everything from systems infrastructure to compliance, risk management, overnight clearing, and performance improvement. 

Please note: this role requires working during 3PM - 11PM GMT / 4PM - 12AM BST hours, with weekends/holidays alternating among the team.

Responsibilities

• Support live crypto trading and other asset classes as needed
• Handle order flow from HRT’s trading desks
• Respond to external market alerts and outages
• Interface with exchanges & other external parties to support trading

Qualifications

• 1-3 years of experience in a similar role or internship
• Bachelor’s degree in a technical discipline
• Working knowledge of UNIX systems, Bash, and Python
• Excellent communication skills and the ability to interface with developers and traders
• Strong organizational skills and meticulous attention to detail
• Excited to work independently in a fast-paced, high pressure environment
• Strong interest in crypto – you follow the digital assets space in your spare time
• Understanding of various financial products, including equities, crypto products, and derivatives is a plus
• Overall interest in market structure and the trading industry
• Series 7 or 57 certification or a willingness to obtain certification
• Ability to work during 3PM - 11PM GMT / 4PM - 12AM BST hours, with weekends/holidays alternating among the team

Hudson River Trading (HRT) is looking for a Junior Electronic Trading Support Engineer to join our global Trade Operations (TradeOps) team in NYC. This team is responsible for managing HRT’s live trading environment, one of the most robust and efficient electronic trading platforms in the world. This includes configuring, monitoring, and optimizing the firm’s trading as well as handling risk, regulatory, and development tasks. The TradeOps team focuses on both automating common tasks and preparing for the unexpected. Your day could consist of debugging to get a process running in time for the market open, making a difficult on-the-spot decision that balances compliance, risk, and PnL during trading hours, or coordinating the technical rollout of a new trading strategy. 

Being a member of TradeOps at HRT means working on a tight-knit, highly productive team. We're looking for someone who loves technology and wants to work on a broad range of projects using whatever tool(s) best solve the problem at hand. Excellent communication is a must, along with a can-do attitude.

Role

In a high performance environment, immediate awareness of and reaction to systems and trading issues is essential. That’s where HRT’s Electronic Trading Support Engineers come in. You’ll be responsible for managing new initiatives and ensuring a smooth trading day. You’ll act as the first line of defense when the inevitable happens, and the subject matter expert on recent changes to the production trading platform. The team’s scope covers everything from systems infrastructure, to compliance, risk management, overnight clearing, and performance improvement. 

Responsibilities 

• Support live trading during US market hours
• Handle order flow from HRT’s trading desks
• Respond to external market alerts and outages
• Interface with exchanges & other external parties to support trading 

Qualifications

• Bachelor’s degree in a quantitative discipline (CS, Engineering, Physics, Math, etc.)
• Working knowledge of UNIX systems
• Experience with a scripting language (Python, Perl, Bash)
• Excellent communication skills and enjoy interfacing with clients, both internal and external
• Incredibly organized, with a high attention to detail
• Excited to work independently in a very fast-paced, high pressure environment
• Poses an understanding of Market Data/Order Entry systems and/or an interest in how modern electronic markets work
• Industry experience and/or Series 7 or 57 certification is preferred if applicable, but not required - recent graduates with relevant knowledge can be considered

The estimated base salary range for this position is 100,000 to 150,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is seeking curious, thoughtful engineers who enjoy working with data and solving real-world technical problems to join our growing Market Structure Analysis team. In this role as a Quantitative Latency Engineer, you’ll apply data-driven methodologies to understand and optimize trading technology and real-time interactions with financial markets across the globe, spanning traditional and crypto exchanges. No prior finance experience is needed! 

Responsibilities

• Contribute directly to impactful improvements to HRT’s low-latency trading systems
• Analyze large datasets to understand how complex systems and networks behave in real-world conditions, such as exchange technology and performance of HRT systems
• Build Python-based tools and scripts to collect, clean, and visualize data in a clear and actionable way
• Design and run experiments to measure the impact of changes and identify opportunities for improvement
• Collaborate closely with HRT’s Algorithm Development, Trading Technology, and Business Development teams to discover, research, and implement improvements to HRT’s architecture
• Liaise with exchanges globally to better understand their technology and stay up to date on changes and improvements

Qualifications

• A technical degree or equivalent practical experience
• Experience with Python and Pandas 
• Proficiency in data analytics including statistics, data visualization, and working with large data sets
• Strong curiosity about how financial systems, networks, and cutting-edge technology work, and a willingness to learn new concepts quickly
• Ability to think analytically, ask insightful questions, and approach unfamiliar problems methodically
• Strong cross-functional communication skills and an interest in collaborating with others

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications 

• Superb debug and analytical skills 
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is looking for an Electronic Trading Support Engineer to join our global Trade Operations (TradeOps) team in NYC. This team is responsible for managing HRT’s live trading environment, one of the most robust and efficient electronic trading platforms in the world. This includes configuring, monitoring, and optimizing the firm’s trading as well as handling risk, regulatory, and development tasks. The TradeOps team focuses on both automating common tasks and preparing for the unexpected. Your day could consist of debugging to get a process running in time for the market open, making a difficult on-the-spot decision that balances compliance, risk, and PnL during trading hours, or coordinating the technical rollout of a new trading strategy. 

Being a member of TradeOps at HRT means working on a tight-knit, highly productive team. We're looking for someone who loves technology and wants to work on a broad range of projects using whatever tool(s) best solve the problem at hand. Excellent communication is a must, along with a can-do attitude.

Role

In a high performance environment, immediate awareness of and reaction to systems and trading issues is essential. That’s where HRT’s Electronic Trading Support Engineers come in. You’ll be responsible for managing new initiatives and ensuring a smooth trading day. You’ll act as the first line of defense when the inevitable happens, and the subject matter expert on recent changes to the production trading platform. The team’s scope covers everything from systems infrastructure, to compliance, risk management, overnight clearing, and performance improvement. 

Responsibilities 

• Support live trading during US market hours
• Handle order flow from HRT’s trading desks
• Respond to external market alerts and outages
• Interface with exchanges & other external parties to support trading 

Qualifications

• Bachelor’s degree in a quantitative discipline (CS, Engineering, Physics, Math, etc.)
• Working knowledge of UNIX systems
• Experience with a scripting language (Python, Perl, Bash)
• Excellent communication skills and enjoy interfacing with clients, both internal and external
• Incredibly organized, with a high attention to detail
• Excited to work independently in a very fast-paced, high pressure environment
• Poses an understanding of Market Data/Order Entry systems and an interest in how modern electronic markets work
• Industry experience and/or Series 7 or 57 certification is preferred

The estimated base salary range for this position is 100,000 to 150,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is seeking a Physical Design Engineer with a broad, versatile skillset to join our growing Hardware team. In this role, you will help deliver performance-critical ASICs and advance our physical design methodologies on leading-edge process nodes.

The Hardware team at HRT builds high-performance compute engines using FPGA and ASIC technology to drive low-latency trading decisions on global markets. We create custom solutions across the full spectrum of speed and sophistication, from bespoke circuits to world-class machine learning accelerators.

Responsibilities

• Drive design-for-test (DFT) methodologies and implementation 
• Contribute to physical implementation, from RTL handoff through GDSII on advanced process nodes 
• Partner on floorplanning and physical optimization for high-performance, latency-critical designs
• Close timing across multiple modes and corners while optimizing power, performance, and area (PPA)
• Diagnose and resolve physical design issues such as timing bottlenecks, congestion, and IR/EM violations
• Build, maintain, and improve repeatable, automated physical design flows
• Develop scripts and tooling to improve productivity, robustness, and insight into design behavior
• Collaborate closely with RTL, architecture, and other hardware engineers to influence design decisions early

Qualifications

• Experience working in high-performance ASIC design environments
• Strong fundamentals in digital logic, circuit design, and process technology
• Familiarity with DFT concepts and testing methodologies
• Strong scripting and automation skills (Python, Tcl, shell), including parsing and analyzing tool outputs
• Ability to design robust methodologies, diagnose complex failures, and improve physical design flows
• Applied use of statistics in analyzing timing, power, or design data (preferred)
• Hands-on experience with static timing analysis and timing closure methodologies
• Expertise using industry-standard physical design and signoff tools (e.g., Innovus, PrimeTime)

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

Hudson River Trading (HRT) is seeking curious, thoughtful engineers who enjoy working with data and solving real-world technical problems to join our growing Market Structure Analysis team. In this role as a Quantitative Latency Engineer, you’ll apply data-driven methodologies to understand and optimize trading technology and real-time interactions with financial markets across the globe, spanning traditional and crypto exchanges. No prior finance experience is needed!

Responsibilities 

• Analyze time series network and exchange protocol captures
• Become familiar with the details of specific markets, attend presentations and liaise with exchange counterparts
• Research exchange features, capabilities, and architecture
• Automate collection and visualization of metrics that quantify efficacy of exchange communication
• Formulate and conduct controlled experiments that measure impact of calculated changes to HRT’s trading infrastructure
• Communicate ideas, requirements, and results across disparate teams
• Improve fill rate of our hardware-based trading strategy
• Reduce incidence of cancel-reject responses
• Investigate and report details of various latency-sensitive exchanges

Profile 

• You possess a degree in Data Analytics or a related field
• You can collect and interpret network and/or financial market data
• You have professional experience in latency reduction, preferably in finance
• You have a basic understanding of proprietary trading and exchange technologies

Skills 

• Proficiency in data analytics including statistics, data visualization, and working with large data sets
• Basic understanding of TCP and UDP network protocols
• Extensive experience with Python and relevant data libraries (Pandas, Numpy/Scipy)
• Some familiarity with the details of modern computer systems and networks
• Experience with real time exchange market data and order entry a plus

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is looking for a Senior Software Engineer to focus on our Treasury Infrastructure. Coders at HRT work on small, highly productive, and efficient teams that design, improve, and maintain the technology that powers worldwide trading — at HRT, the code you write is our business. You’ll have an opportunity to work closely with Treasury Quantitative Researchers and our Funding Team to design and develop HRT's Treasury Optimization and Research Platform.

We are looking for highly skilled programmers who love to code and solve complex problems, appreciate a culture of collaboration, and thrive in a performance-driven environment. You can always expect to be challenged by the ever-changing financial markets, and find yourself working on critical software in an extremely fast-paced, real-time environment.

Responsibilities

• Contribute to the engineering design and development of HRT’s Treasury Optimization Platform.
• Collaborate with Treasury Researchers on HRT’s Treasury Research Infrastructure.
• Collaborate with Quantitative Developers as well as our Funding and Finance teams on managing cash and collateral requirements.

Qualifications

• Completed a Bachelor's or Master's degree in Computer Science, Engineering, or a related technical field. If you are currently pursuing your Bachelor's degree, please apply to our Campus/New Grad opportunities.
• Working experience in Python and good CS fundamentals.
• Proficiency with numerical computing libraries (Numpy, PyTorch, TensorFlow) is a plus.
• Knowledge of global portfolio financing and funding is a plus.
• Strong problem-solving skills and ability to work in a fast-paced environment.
• Excellent communication skills and ability to collaborate with engineers, researchers, and non-technical teams.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is a quantitative trading firm at the forefront of technological innovation. We build and deploy cutting-edge systems within one of the world’s most advanced computing environments to power our global trading operations. Our non-siloed, collaborative coding environment empowers talented engineers to make significant contributions and see their impact daily. At HRT, you'll be challenged to solve the most complex problems in trading alongside many of the brightest minds in the field.

We are seeking highly motivated and skilled Research Engineers who will work very closely with our Algo Developer (Quant Research) trading teams. These roles require exceptional programming fundamentals, a strong user focus, and the ability to thrive in a fast-paced environment with constantly evolving requirements. Multitasking and context switching are inherent aspects of this role, through which you will gain insight into the ideation and execution of some of the world's most sophisticated trading strategies.  

Research Engineers at HRT work on a wide variety of projects. Examples include:

• Designing highly customized quantitative systems that enable Algo Developers to easily express and backtest new predictive signals.
• Building world-class research tooling to speed up Algo Developers’ research iteration.
• Aiding the development and deployment of very large deep learning models for HRT’s live trading.
• Improving HRT’s monetization systems which turn our predictions into profitable trades.
• Evaluating sim vs. live differences to improve the fidelity of our simulations.
• Building systems to monitor and manage live trading.
• Specializing in specific time horizons, from high frequency trading to mid-to-low frequency hedge fund-style strategies.
• Working across a very wide variety of asset classes (from equities to fixed income to options) and regions (from North America to Asia Pacific) – you’ll interact with markets across the world!

Responsibilities

• Design, develop, and maintain robust, performant, and scalable software systems.
• Optimize existing codebases for performance, reliability, and efficiency.
• Debug complex issues across distributed systems in a time-sensitive environment.
• Optimize both the mechanics and ergonomics of Algo Developer research workflows; this requires developing a deep intuition for research methodologies.
• Balance the short term goals of individual trading teams with the longer term goals of HRT’s generalized trading platforms across trading teams. Because we don’t work in a pod environment, REs on different trading teams are expected to share technology and ideas.

Qualifications

• Completed a Bachelor's or Master's degree in Computer Science, Engineering, or a related technical field. If you are currently pursuing your Bachelor's degree, please apply to our Campus/New Grad opportunities.
• Previous experience at a top-tier finance or technology company with an excellent track record of rapid advancement and superlative reviews.
• Experience with supporting internal users is preferred; bonus if you have real hands-on experience with quant research and/or ML/Deep Learning platforms.
• Experience with python numerical, ML and data-oriented libraries is a big plus (e.g. pandas, scikit, pytorch, etc.)
• Candidates should be prepared for technical interviews in either Python or C++. While there is no hard language requirement for RE roles, proficiency in one of these languages will be assessed during the interview process.
• Kindness and empathy is a real requirement. No “smart jerks” at HRT. 
• Strong understanding of data structures, algorithms, and design principles.
• Excellent communication skills, both written and verbal.
• HRT ships every day. The ability to thoughtfully, methodically, and reliably deploy new software and features is a critical skill. 
• If you have management experience, that’s always a bonus – but even so, expect to code!

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

For more info about interviewing at HRT, see this blog!

Working as a coder at Hudson River Trading (HRT) means working on a small, highly productive, and efficient team. You may see "trading" in our name and assume you'll be relegated to some dark corner to code for the "business," but that could not be further from the truth! 

At HRT, an automated trading firm based in NYC, the code you write *is* our business, so it is everyone's job to make sure our developers have everything they need to do their jobs well.

As a member of the AI Tools team, you will be responsible for increasing productivity across the company by integrating the newest AI tools into our users’ workflows. Whether it’s for a Python developer writing a web app, a C++ developer speeding up order execution, a researcher investigating trade signals, or even Business Development meeting with vendors - we are focused on deploying what works.

This is an exciting opportunity to help build and define the AI tooling ecosystem at HRT. You will have to navigate the rapidly evolving options in this space, and adapt them to our own internal systems. You might be fixing auth one day, comparing vendors the next, and coding a new MCP the third. 

Responsibilities

• Help us develop software that improves productivity for every office and department at HRT while using the latest technologies and techniques in software engineering and the broader AI tooling ecosystem.
• HRT has many high-impact areas where we are integrating AI tools; here’s what you could work on:
• Writing a custom MCP wrapper around internal resources.
• Fine-tuning a new code completion model.
• Deploying a new coding assistant across all developer and researcher environments.
• Developing evaluations and iterating on an autonomous coding agent.
• Collaborating with security to improve AI sandboxing.
• Presenting and educating users on best practices.

Profile

• You’re one of the top devs in your current organization, as measured by productivity, technical capability, and helpfulness to other devs.
• Experience deploying and maintaining applications. You’ve managed an application from the design phase through the production phase.
• You’re comfortable with defining direction in an environment of ambiguity and uncertainty. The AI tooling space changes rapidly.
• You really like to work with people who challenge you and make you better at what you do.
• In your spare time you code, tinker, read, explore, break things, and have an insatiable curiosity for all things AI and computer-related.

Qualifications

• Completed a Bachelor's or Master's degree in Computer Science, Engineering, or a related technical field. If you are currently pursuing your Bachelor's degree, please apply to our Campus/New Grad opportunities.
• Python experience is required, daily use of most recent standards preferred.
• C++ and JavaScript (TypeScript, React) experience a plus.
• Experience with the AI tooling ecosystem (use coding assistants/agentic workflows, ideally have built your own customizations).
• Superior design, debugging, and problem solving skills.
• Knowledge of UNIX operating systems (we use Linux), system/processor performance, and network communication.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

At Hudson River Trading (HRT), C++ is at the center of our live trading systems and research infrastructure. Our C++ engineers build the highly performant, fault-tolerant systems that power trading across global markets. HRT’s distributed system is on the Pareto frontier of latency and throughput, giving you limitless opportunity to leverage your deep knowledge of C++, OS internals, CPU architecture, and networking hardware and protocols. You’ll work side-by-side with researchers, traders, and hardware specialists, implementing solutions where every microsecond matters.

Our bottom-up approach to projects and our highly collaborative environment empower talented engineers to make significant contributions and see their impact daily. At HRT, you'll be challenged to solve complex problems in a fast-paced, highly competitive industry, surrounded by some of the brightest minds in the field.

C++ Engineers at HRT work on a wide variety of projects. Examples include: 

• Develop and optimize infrastructure for market data, order entry and execution logic, spanning tens of asset classes including options, equities, futures, crypto, and fixed income. 
• Design fault-tolerant, low-latency systems for live trading, including encoding/prioritization of data over WAN links and recovery from hardware failures.
• Profile and improve performance-critical code for both throughput and latency in production environments.
• Build and maintain infrastructure that drives products including client-facing wholesale and SDP platforms, distributed network filesystems, and scalable research workflows.
• Write software that interfaces with specialized hardware such as FPGAs and ASICs used in trading systems.

Profile

• You’re one of the top devs in your current organization, as measured by productivity, technical capability, and helpfulness to other devs.
• You are capable of solving complex engineering problems independently and providing technical advice for others in areas of your expertise. 
• You can make progress on long-term architectural projects while troubleshooting smaller tasks and bug fixes with agility.
• You can describe software designs at a high level (the abstract interface), low level (step-by-step algorithm), or anywhere in between. 
• You are always looking for ways to make systems better.

Qualifications

• 1+ years of professional work experience 
• Bachelor's degree in Computer Science, Computer Engineering, or related field
• Superior design, debugging, and problem solving skills
• Advanced C++ experience is required, daily use preferred
• Knowledge of UNIX operating systems (we use Linux), system/processor performance, and network communication

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is one of the top algorithmic trading companies in the world. Our research cluster is the backbone of our success; it’s where all of our trading strategies are generated.

We use a large, customized research environment with highly advanced CPU and GPU compute, storage, and networking technology. Our team thinks about the entire software stack, from the user-level API to optimizing performance out of low-level caching. We deal with everything from the theoretical, like fair resource scheduling, to the concrete, like optimizing a trader’s new program run-time performance. 

As a distributed compute engineer in a user-facing environment, you’ll develop and improve on technical solutions that make research as easy and efficient as possible. You’ll work everyday with both talented quantitative traders and software engineers across all trading teams.

Responsibilities

• Ensure HRT’s research environment is best in class, with a focus on user workloads
• Maintain and improve resource scheduling, data caching, and job monitoring to make research as easy, fast, and efficient as possible, using both in-house and open source solutions
• Optimize workloads at the user level to speed up user iteration speed
• Tune workloads at the infrastructure level to make them more resource-efficient
• Share metrics and real-time information with users to give insight into workload behavior
• Sit down with users to understand their specific technical needs
• Contribute individually and through leadership and coordination of the above
• Set technical direction for the platform and take holistic ownership of the software infrastructure that supports Algo research

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or a related field
• Strong C++ expertise (daily use preferred)
• Python familiarity preferred
• Experience collaborating closely with quantitative researchers and traders to understand their needs
• Great communication capabilities
• Superior design, debugging, and problem solving skills
• Knowledge of UNIX operating systems (we use Linux), system/processor performance, and network communication

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is a leading quantitative trading and investment firm specializing in multi-asset class strategies. At the core of our success lies the power of our compute cluster, the foundation where all our trading strategies are conceived and refined.

We’re looking for innovative minds to enhance the data storage libraries and tools leveraged by our Research teams to generate cutting-edge strategies. As a Storage Developer, you’ll dive deep into C++ and advanced storage solutions, working at massive scale to enable groundbreaking research. Surrounded by a team of exceptional developers constantly pushing the boundaries of their expertise, you’ll be amazed at the impact you can achieve.

Profile

• You’re able to talk both high-level distributed systems design trade-offs and low-level OS-level details
• You’re able to balance being detail-oriented with good prioritization of what matters now vs. later
• You thrive in collaborative environments and have a strong sense of ownership
• In your spare time you code, tinker, read, explore, break things, and have an insatiable curiosity for all things computer related

Responsibilities

• Work with a small team of skilled developers to create distributed storage systems customized to fit HRT’s needs
• Stay informed about the current “state of the art” and help bridge the gap between here and there
• Understand our Research team’s storage and compute needs, and build for the next generation of research

Qualifications 

• Proficient C++ experience is required, daily use preferred 
• Distributed systems experience required (ability to reason about fault tolerance, sharding, trade-offs, and designing for simplicity and robustness under failure) 
• Previous experience developing databases, distributed filesystems, search infrastructure, or similar ideal but not required 
• Ability to work productively in a Linux environment
• Knowledge of UNIX operating systems, low-level systems-level performance issues, and networking

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is a quantitative trading firm at the forefront of technological innovation. We build and deploy cutting-edge systems within one of the world’s most advanced computing environments to power our global trading operations. Our bottom-up approach to projects and collaborative coding environment empower talented engineers to make significant contributions and see their impact daily. At HRT, you'll be challenged to solve the most complex problems in trading alongside many of the brightest minds in the field.

We are always seeking highly motivated and skilled Software Engineers across many different teams at HRT. These roles demand exceptional programming fundamentals, sharp debugging abilities, and strong critical thinking and communication skills. Engineers at HRT work on a wide variety of platform and trading-adjacent projects. Examples include:

• Improving scheduling efficiency of distributed computations, speeding up research iteration.
• Enhancing developer experience through language tooling, jupyter extensions, and AI tools.
• Leveraging LLMs to make operational support tasks faster and more efficient.
• Profiling computer usage at all levels, from system calls to large scale distributed computations.
• Building systems to interact with trading venues and monitor risk.

Responsibilities

• Design, develop, and maintain robust, efficient, and scalable software systems.
• Debug complex issues across distributed systems in a time-sensitive environment.
• Contribute to all phases of the software development lifecycle, from ideation to deployment and support.
• Deliver exceptional experiences for internal users; your success will be directly tied to your ability to understand the needs of the people around you and apply your technical skills to efficiently meet them.

Qualifications

• Completed a Bachelor's or Master's degree in Computer Science, Engineering, or a related technical field. If you are currently pursuing your Bachelor's degree, please apply to our Campus/New Grad opportunities.
• Previous experience at a top-tier finance or technology company with an excellent track record of rapid advancement and superlative reviews.
• Experience with applications of cutting-edge technology is preferred; being a core contributor to said technology is even better.
• Candidates should be prepared for technical interviews in Python. While there is no hard language requirement for these roles, proficiency in one this language will be assessed during the interview process.
• Kindness and empathy is a real requirement. No “smart jerks” at HRT. 
• Strong understanding of data structures, algorithms, and design principles.
• Excellent communication skills, both written and verbal.
• HRT ships every day. The ability to thoughtfully, methodically, and reliably deploy new software and features is a critical skill. 
• If you have management experience, that’s always a bonus – but even so, expect to code!

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

For more info about interviewing at HRT, see this blog!

Hudson River Trading (HRT) is seeking a Trading Systems Engineer to join our growing Trading Systems Infrastructure team. This team designs, builds, and maintains the infrastructure that powers our global trading, and is responsible for ensuring optimal performance and uptime of the ultra low-latency operating systems, automation software, and development tools that allow our trading strategies to run worldwide 24/7.

As a Trading Systems Engineer, you’ll work on projects focusing on our real-time production trading environment and tackle problems that require high availability, high throughput, and ultra low-latency solutions. The ideal candidate possesses a passion for coding and automation, is eager to learn new skills to help build an elegant stack, and has the ability to handle challenging technical issues within a dynamic and fast-paced environment.

Responsibilities

• Design, manage, automate, and optimize worldwide Linux-based trading infrastructure by planning and executing complex technical projects and tasks
• Troubleshoot hardware and software issues across the stack 
• Design and implement system installations and upgrades 
• Deploy, configure, and test internal and external applications 
• Remain unfazed by production-critical issues, resolving them quickly and efficiently
• Benchmark and tune the performance of the trading stack 
• Hold vendors accountable on performance and reliability issues, with the ability to confidently go toe-to-toe with a vendor's Tier 2 engineering team during an escalation
• Join an on-call rotation schedule to cover trading hours and weekend shifts, as needed

Qualifications

• 7+ years of relevant experience supporting a live production environment (especially trading)
• Expert in installing, configuring, and troubleshooting Linux systems, from hardware and networking to kernel to applications 
• Knowledge of Debian/Ubuntu is desirable
• Proficiency with configuration management tools, particularly SaltStack – strong knowledge of Puppet, Ansible, Chef, or CFEngine is also desirable
• Advanced programming experience focusing on automation and integration; Python is strongly preferred
• Advanced shell (bash) scripting experience
• Significant experience managing and debugging production trading services
• Strong cross-functional communication and organization skills
• Proven ability to manage assigned projects efficiently, ideally using JIRA
• Architect-level cloud experience in AWS or GCP is desirable, but not required

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 150,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

JOB SUMMARY

We are seeking a highly skilled and experienced Staff Compute Engineer to lead the design and implementation of the next-generation compute solution for our humanoid robot platform. In this pivotal role, you will be the technical lead responsible for architecting a compute solution that meets our most demanding requirements for real-time performance, sensor bandwidth, and, most critically, functional safety.

ESSENTIAL DUTIES AND RESPONSIBILITIES or KEY ACCOUNTABILITIES

• Lead the architectural design of the robot's next-generation compute solution, from high-level system architecture to component-level selection.
• Define and validate compute requirements based on the needs of complex robotics algorithms, including motion control, perception, and AI tasks.
• Develop a robust and scalable solution capable of handling high-bandwidth data from a wide array of sensors
• Design for functional safety from the ground up, implementing redundant systems, fail-safe mechanisms, and diagnostic features to meet or exceed industry safety standards.
• Collaborate closely with cross-functional teams, including software, electrical, and systems engineers, to ensure seamless integration of the compute solution with the overall robot platform.
• Conduct performance benchmarking and power analysis to optimize the compute stack for maximum efficiency and thermal management.
• Design, simulate, implement, and test multi-layer high-speed PCBs for integration of advanced System-on-Modules (SoMs) like NVIDIA Orin.
• Lead efforts in high-speed signal integrity (SI) and power integrity (PI) analysis, modeling, and validation.
• Knowledge of compute and processor power requirements, power trees, PMICs, and power sequencing.
• Drive the selection and qualification of critical components, including SoMs, memory, storage (NVMe/eMMC), high-speed interconnects, and peripheral interfaces.
• Develop comprehensive validation and test plans (DVT/PVT), design necessary test fixtures, and execute rigorous testing to confirm compliance with performance specifications and regulatory standards (e.g., FCC, CE).
• Stay abreast of the latest advancements in embedded systems, real-time operating systems (RTOS), and robotics compute hardware to inform future design decisions.
• Own the entire lifecycle of complex compute hardware systems, from initial concept and architecture definition through design, prototyping, validation, production release, and ongoing support.
• Act as a technical leader and mentor within the electrical engineering team, guiding junior and senior engineers on best practices for complex hardware design and troubleshooting.

SKILLS AND REQUIREMENTS

• Proven experience in architecting and shipping complex, high-performance compute solutions for robotics, autonomous systems, or similar applications.
• Deep understanding of functional safety principles and standards (e.g. IEC 61508) and experience with safety-critical design.
• Expertise in a variety of compute platforms, including but not limited to, NVIDIA Jetson, Intel, and other high-performance embedded systems.
• Strong knowledge of real-time operating systems (RTOS), multi-core processing, and communication protocols (e.g., Ethernet, CAN).
• Experience with sensor bandwidth management and high-speed data transfer.
• Excellent problem-solving skills and a collaborative approach to engineering.
• Experience with humanoid robotics is a significant plus.

EDUCATION and/or EXPERIENCE

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field; Master's or Ph.D. preferred.
• 10+ years of experience in embedded systems or robotics compute design.

PHYSICAL REQUIREMENTS: 

• Prolonged periods of sitting at a desk and working on a computer 
• Must be able to lift 15 pounds at times 
• Vision to read printed materials and a computer screen 
• Hearing and speech to communicate

The Role

As a Staff Wire Harness Engineer, you are the principal technical authority for the "nervous system" of our humanoid platform. You don't just design harnesses; you define the interconnect architecture that enables Apollo to move, sense, and think. This role requires a rare blend of deep electrical knowledge , mechanical integration, and strategic leadership. You will own the technical roadmap for power and data distribution, ensuring our systems are not only robust but also optimized for mass production and field serviceability.

Responsibilities

• Interconnect Architecture: Define the top-level electrical distribution strategy for the entire robot, including grounding schemes, shielding architecture, and power/data separation protocols.
• Joint-Crossing Lifecycle Leadership: Own the technical strategy for harness routing across high-DOF joints. Develop and validate mathematical models for cable life expectancy (millions of cycles) and select materials that survive extreme dynamic environments.
• Standardization & Tooling: Establish company-wide standards for E-CAD workflows, library management, and drawing requirements. Lead the selection and implementation of enterprise-level harness design software (e.g., Zuken E3, Capital).
• Cross-Functional System Design: Act as the primary technical bridge between EE, MechE, and Manufacturing. Lead high-level trade-off analyses regarding connector density vs. serviceability and mass vs. thermal performance.
• DfX: Drive Design for Excellence (DfX) initiatives to reduce harness complexity, part count, and assembly time. Evaluate and qualify advanced techniques like overmolding, ultrasonic welding, and custom busbars.
• Root Cause & Reliability: Lead failure analysis for the most complex system-level electrical issues. Use advanced diagnostic tools and DFMEAs to identify and mitigate "hidden" failure modes in signal integrity or power transients.
• Vendor & Supply Chain Strategy: Partner with Sourcing to vet and manage strategic harness manufacturing partners, ensuring our technical requirements are met during the transition from prototype to high-volume production.
• Mentorship: Provide technical leadership and mentorship to junior and senior engineers, conducting deep-dive design reviews and fostering a culture of technical excellence.

Qualifications

• Experience: Bachelor’s or Master’s degree in EE, ME, or Robotics with 8+ years of experience in complex electromechanical systems. 
• Subject Matter Expertise: Expert-level knowledge of High-Speed Data and High-Power  distribution within a single, space-constrained harness.
• Dynamic Routing: Proven track record of designing harnesses for high-cycle dynamic applications (robotics, aerospace gimbals, or automotive doors/hatches).
• E-CAD Mastery: Advanced proficiency in Zuken E3.series, Siemens Capital, or SolidWorks Electrical, including database management and automated report generation.
• Physics-Based Design: Deep understanding of EMI/EMC mitigation, shielding effectiveness, and thermal derating of conductors in bundled configurations.
• Communication: Ability to distill complex technical trade-offs into actionable recommendations for executive leadership.
• Industry Standards: Deep familiarity with IPC-WHMA-620 and related aerospace/automotive quality standards.
  
  

PHYSICAL REQUIREMENTS 

• Prolonged periods of sitting at a desk and working on a computer
• Must be able to lift 15 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate

Scope

Ambiq is seeking an Edge AI Firmware Engineer to build and optimize the embedded software stack that powers real-time, battery-powered on-device AI. You will develop Ambiq’s AI runtimes, performance-critical operator libraries, and profiling/debug tooling that enable customers to deploy efficient inference on resource-constrained devices.

While the cloud has been the default home for AI, the next frontier is distributing intelligence everywhere—directly onto real-world devices. Edge AI enables real-time responsiveness, stronger privacy, lower bandwidth cost, and reliable operation even without connectivity. This role helps accelerate the shift to on-device intelligence across a rapidly growing ecosystem of health and fitness wearables, smart glasses, industrial IoT, and always-on sensors.

You’ll work closely with platform, silicon, and applied ML teams—and directly with customers—to ensure our software extracts maximum performance and energy efficiency from Ambiq hardware while remaining easy to integrate into production embedded toolchains.

Responsibilities 

• Develop and support Ambiq’s embedded AI runtimes (HeliaRT—our fork/extension of TensorFlow Lite for Microcontrollers—and HeliaAOT) with focus on portability, correctness, performance, and usability.
• Implement and optimize ML operator kernels and embedded libraries for on-chip acceleration (DSP, vector, NPU), including HeliaDSP and HeliaCore components.
• Build and maintain on-device profiling and performance analysis tools, including converting PMU counters into actionable insights.
• Drive improvements in latency, memory footprint, and energy (e.g., joules/inference) through compute/bandwidth and memory-hierarchy analysis.
• Develop benchmark harnesses, microbenchmarks, and regression tests to ensure numerical correctness and prevent performance regressions.
• Enable seamless customer integration across embedded environments and toolchains (bare metal, FreeRTOS, Zephyr).
• Improve memory planning/runtime efficiency and manage upstream/fork health; publish and maintain customer-facing assets (docs, guides, examples, benchmarks).

Qualifications 

• BS in Electrical/Computer Engineering, Computer Science, or related field + 5+ years relevant experience (or equivalent practical experience). MS is a plus, especially in embedded systems, compilers, computer architecture, or ML systems.
• Strong experience designing, developing, and testing embedded software in C/C++.
• Strong debugging discipline with an emphasis on correctness, reproducibility, and performance regression prevention.
• Solid understanding of compute, memory, and bandwidth/cache effects on deterministic latency and energy efficiency in constrained systems.
• Ability to interpret hardware/software documentation (datasheets, reference manuals; schematics a plus).
• Proficiency with Git (or equivalent version control).
• Efficient use of AI-assisted development tools to improve productivity while maintaining engineering rigor.
• Experience with embedded development workflows: Arm toolchains, GDB + J-Link/SEGGER-class probes, and CMake/Make build systems.

Nice to have:

• Python for profiling/analysis tooling, automation, and developer utilities.
• Rust experience.
• Familiarity with TensorFlow Lite for Microcontrollers (or similar embedded inference runtimes).
• Experience optimizing for embedded acceleration targets (e.g., DSP, vector extensions, NPU).
• Familiarity with CMSIS-NN, CMSIS-DSP, and/or Vela (or similar).
• Working knowledge of quantized inference (e.g., int8, per-channel) and embedded debugging implications.
• Packaging/integration (e.g., CMSIS-Pack/CPM.cmake) and/or lab measurement experience (power/debug with basic bench tools).

Must be currently authorized to work in the United States for any employer. We do not sponsor or take over sponsorship of employment visas (now or in the future) for this role.

We are looking for a Staff Security Software Engineer who is passionate about detecting and mitigating abuse in the Cloud. 

As a Staff Security Software Engineer at DigitalOcean, you will join a dynamic team dedicated to revolutionizing cloud computing and AI. This role reports to the Senior Manager of Security Engineering within the Security organization. You should have experience developing and maintaining software systems in a complex, high-scale environment, analyzing outcomes and communicating insights to stakeholders, and rapidly devising solutions that are in alignment with overall business goals. Our team is focused on enabling DigitalOcean to scale safely by building systems that detect and prevent abuse on our platform. We highly value collaboration and growth, and work closely with other teams in the Security organization to deliver high quality solutions and also build tooling to boost their efficiency.

Our customers trust us with their data and operations, and we take that responsibility seriously. Security at DO means solving highly complex problems on a large scale that have real impact for our customers, our products, and for the larger internet community.

What You’ll Do:

• Design, develop, and deploy resilient services and tooling that provide security capabilities at scale, primarily in Go, with some work in Javascript and Python.
• Research and design automated approaches to detecting and actioning abuse and misuse of DigitalOcean products and services.
• Work with product and engineering teams to design and implement secure architectures.
• Design and build internal tools that enable our Security Operations Center to do more, faster.
• Measure the efficacy of our services and tools, using logs, metrics, and audit records, to drive reporting and decision-making, leading to iterative and transformative security improvements as DigitalOcean scales. All while being mindful that security should be an efficiency enabler for the business, not an obstacle.

What You’ll Add to DigitalOcean:

• 8+ years of hands-on experience in software engineering projects, ideally with a security focus, in a complex, high-scale SaaS or IaaS environment. You are an expert in writing robust code with good test coverage and demonstrated success in delivering projects.
• Understanding of cloud-native services and infrastructure provisioning (e.g. compute, storage, networking).
• Deep familiarity with cloud services & infrastructure—compute, storage, network, managed services—and related abuse tactics, including DDoS, spamming, phishing, cryptomining, and bot networks.
• Strong analytical and reporting skills, with proficiency in SQL and data warehouse querying (e.g., Snowflake, Redshift, BigQuery)
• A customer-first mindset—you aim to maximize abuse prevention while avoiding false-positives that could impact high-value customers.
• Excellent communication and documentation skills; you can clearly articulate patterns, mitigation strategies, and tradeoffs to both technical and non-technical stakeholders. You have a record of partnering with internal engineering teams and non-technical stakeholders to gather requirements and tackle security problems across an entire stack with empathy and creativity.
• High integrity, strong judgment, and a track record of working independently on high-impact investigations and policy decisions.

Bonus qualifications:

• Experience with microservice architectures, asynchronous and event-driven processing, and synchronous gRPC/HTTP-based requests.
• Experience in building secure by default services and applications.
• Familiarity with technologies such as gRPC, Docker, Elasticsearch, Prometheus/VictoriaMetrics, Kubernetes, and GitHub Actions.
• Experience with Looker, Snowflake, dbt, and Airflow

Compensation Range: 

• $166,400 - $208,000

*This is a remote role

#LI-Remote

We believe in leveraging the best tools to solve problems faster. You will be expected to utilize AI coding assistants and LLMs proficiently to accelerate development velocity, generate boilerplate, and troubleshoot complex debugging scenarios. Beyond simple usage, this role requires the critical judgment to verify AI-generated outputs for security, performance, and accuracy. You should be comfortable integrating AI tooling into your daily workflow to eliminate repetitive tasks, allowing you to focus on high-impact architectural and strategic engineering challenges.

A Staff Software Engineer at Realtor.com is a technical leader that focuses on ambiguous problems for the squad. You will also:

• You help and guide the team in making the right trade-offs between short-term requirements and the long-term business/operational success of the squad. 
• You provide system-wide view and design guidance to the squad members and also influence the design decisions made by other teams. 
• You help the team to make trade-offs and re-use where possible.
• You work on project ideas with Product Management and engage with customers, stakeholders, and peers. 
• Your code submissions and approach to work are exemplary. 
• You mentor by actively participating in the code review process, design discussions, and team planning.

What will you do?

• Lead the design and delivery for the ambiguous/complex problem space in the squad.
• Provide guidance to team/s on system architecture and design.
• Develop solutions that are of high quality, scalable, and reliable
• Work collaboratively in squads composed of Product Managers, Designers, Analysts, and Engineers.
• Mentor and develop a team of engineers
• Investigate and prototype technologies that can be leveraged to introduce new innovations
• Be self-directed, take initiative and drive towards solutions with little guidance

What will you bring?

• Bachelor’s degree in Computer Science or equivalent experience
• 8+ years experience in software development
• 3+ years of experience contributing to architecture and design
• Experience in building software or interest and ability to learn in the Realtor.com® stack of Python (FastAPI, Pydantic, Numpy, Pandas) and React
• Experience with database systems and AWS knowledge preferred
• Experience delivering high value to customers quickly, frequently, with regular feedback and support
• Experience with system design and trade-offs between design approaches
• Strong software engineering best practices (e.g. testing, code reviews, documentation).

How we Reward you:

Realtor.com® is committed to investing in the health and well-being of our employees and their families. Our benefits programs include, but are not limited to:

• Inclusive and Competitive medical, Rx, dental, and vision coverage
• Family forming benefits
• 13 Paid Holidays
• Flexible Time Off
• 8 hours of paid Volunteer Time off
• Immediate eligibility into Company 401(k) plan with 3.5% company match
• Tuition Reimbursement program for degree and non-degreed programs
• 1:1 personalized Financial Planning Sessions
• Student Debt Retirement Savings Match program
• Free snacks and refreshments in each office location

Job Summary

We're looking for an experienced staff electrical engineer to own the electronics EMI/EMC design and test strategy as well as RF communication subsystems for the Apollo humanoid robot. We are primarily interested in candidates who have developed and released products to the market in robotics, automotive, medical, personal electronics, or enterprise spaces. In this job role, you will own the strategy for requirements, design, and testing of RF, EMI, and EMC for the electrical systems in and around Apollo.

Responsibilities

• Develop and execute comprehensive validation and test plans, design necessary test fixtures, and execute rigorous testing to confirm compliance with performance specifications and regulatory standards (e.g., FCC, CE, UL).
• Own architecture and component selection for RF communication subsystems.
• Collaborate with leadership, program management, and cross-functional teams to plan and execute company strategy.
• Innovate by bringing new core technologies, test practices, and processes into electrical engineering developments.
• Define, simulate, and verify electronics and electrical system requirements.
• Design, simulate, implement, and test multi-layer mixed signal PCBAs.
• Rapid prototyping of electrical systems at both system and board levels.
• Generate design documentation such as schematics, block diagrams, test plans and procedures, fabrication and assembly drawings.
• Design hardware to meet functional safety requirements, implementing redundant systems, fail-safe mechanisms, and diagnostic features to meet or exceed industry safety standards.
• Conduct performance benchmarking and power analysis to optimize the hardware for maximum efficiency and thermal management.
• Participate in the debugging and root cause analysis related to hardware and software defect resolution.
• Own the entire lifecycle of electronics and electrical systems from initial concept and architecture definition through design, prototyping, validation, production release, change requests, and ongoing support.
• Mentor junior and senior engineers.
• Manage 3rd party relationships with vendors, contract manufacturers, and external design services.

Qualifications

• Bachelors, Masters, or PhD degree (or equivalent) in Electrical Engineering or related field.
• 8+ years of experience in electronics development.
• Demonstrated experience taking a product through FCC (Part 15b) and CE radiated and conducted emissions testing.
• Experience with 47 CFR 15.109 and IEC 61000-6 series standards.
• Experience with RF module selection and integration, particularly for 2x2 (or 4x4) Triband Wifi (5, 6, 6E, 7), high-throughput/data rate wifi systems, mobile device RF design, cellular 5G (carrier and private).
• Experience with wifi drivers for IEEE 802.11.
• Experience with antenna integration. Can inform on antenna selection or design, antenna placement, and interaction of antennas and surrounding materials.
• Experience with RF system performance optimization (mixed HW / SW / FW configuration).
• Excellent communication (verbal & written); will be expected to develop detailed build assembly instructions and diagrams.
• Excellent problem-solving and hardware debugging skills.
• Hands-on experience with prototyping and testing, including the use of lab equipment.
• Experience with robotics or designing electronics for lightweight, space-constrained systems is a significant plus.
• Nice-to-have: RF firmware/software experience, Nvidia Orin NX, Nvidia Orin AGX, Mobile robotics experience is a plus (antennas on robot vacuums or industrial AMRs), Intel Wi-Fi 6 AX201.

PHYSICAL REQUIREMENTS

• Prolonged periods of sitting at a desk and working on a computer 
• Must be able to lift 15 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate

JOB SUMMARY

We are seeking a Staff Test Engineer – Actuation to own the design validation and NPI test process for Apptronik's custom actuator systems. This is a hands-on, multi-disciplinary role spanning mechanical, electrical, firmware, and software testing — requiring someone who can independently drive actuator characterization and validation from initial bringup through design verification, and build the test methods and automation that transfer to test ops as programs move into production.

You will design and execute actuator test campaigns, develop robust bringup and calibration workflows, diagnose hardware issues across the full electromechanical stack, and deliver validated, well-documented test processes that are ready for handoff. You will work closely with mechanical, electrical, firmware, and controls engineers — connecting test data to root-cause analysis and hardware design improvements.

KEY RESPONSIBILITIES

• Actuator Bringup & Calibration: Lead the bringup process for new actuator hardware — including firmware deployment, motor and encoder calibration, and functional verification. Develop documented, repeatable procedures that can be transferred to test ops for production use.
• Design Validation Testing: Plan and execute design validation campaigns to characterize actuator performance across the operating envelope. Tests span mechanical (e.g., efficiency, stiffness, backlash, life), electrical (e.g., peak current, thermal limits, drive performance), and system-level (e.g., positional accuracy, off-axis loading, effort production) domains.
• Test Method Development for Production: Design and validate the production test methods used during NPI — including test scripts, post-processing, pass/fail criteria, and operator documentation — then hand off to the test ops team with the tooling and training needed to run them at scale.
• Test Automation & Data Infrastructure: Build Python-based test automation, data pipelines, and analysis tools that enable repeatable, scalable validation across multiple actuator types and hardware revisions.
• Test Equipment Operation: Operate and configure dynamometer, benchtop, and custom test setups. Manage fixture configurations and load motor modes across different actuator and gearbox variants.
• Cross-Stack Root-Cause Analysis: Diagnose actuator performance issues spanning firmware, electrical, and mechanical domains using structured, data-driven reasoning. Provide clear, actionable feedback to design teams.
• System Identification: Apply system identification techniques to characterize actuator dynamics — including inertia, friction, bandwidth, and torque constant — providing data that supports both hardware validation and simulation fidelity.
• Collaboration & Reporting: Work closely with mechanical, electrical, firmware, and controls engineers. Communicate test results, failure modes, and recommendations clearly to engineering and program leadership.

SKILLS AND REQUIREMENTS

Required Qualifications

• Direct hands-on experience testing and characterizing actuators, motors, or gearboxes — including operation of dynamometer or motor test stand systems.
• Experience with motor bringup and calibration workflows, with enough firmware and electrical fluency to diagnose calibration and drive faults independently.
• Strong cross-disciplinary debugging ability across mechanical, electrical, and firmware domains.
• Proficiency writing production-grade Python for test automation, data analysis, and post-processing.
• Demonstrated experience designing test methods and procedures — including pass/fail criteria and handoff documentation — not just executing pre-written scripts.
• Ability to read and interpret electrical schematics, mechanical drawings, and motor datasheets.
• Experience working in multi-disciplinary hardware teams with fast iteration cycles.
• Comfortable operating at staff level: leading technical workstreams, influencing engineering decisions with data, and mentoring others.

Preferred Qualifications

• Experience with humanoid or legged robot actuator systems.
• Familiarity with thermal modeling and thermal test methods for electric motor systems.
• Knowledge of motor drive electronics, power electronics, and power stage design margins.
• System identification background: frequency-domain analysis, bandwidth measurement, and dynamic model extraction.
• Experience transitioning test methods from R&D into production or manufacturing environments.
• Simulation experience (MuJoCo, Isaac Sim/Lab, etc.) and sim-to-real validation workflows.
• Docker, scripting, or infrastructure tooling for test automation at scale.

EDUCATION AND/OR EXPERIENCE

• BS in Mechanical Engineering, Electrical Engineering, Robotics, Computer Science, or related field + 6 years of relevant experience, OR
• MS in related field + 4 years of relevant experience, OR
• PhD in related field + 2 years of relevant experience.

Candidates with non-traditional backgrounds who can demonstrate equivalent hands-on experience with actuator testing and robotic hardware bringup are strongly encouraged to apply.

PHYSICAL REQUIREMENTS

• Prolonged periods of sitting at a desk and working on a computer.
• Must be able to lift 15 pounds at times.
• Vision to read printed materials and a computer screen.
• Hearing and speech to communicate.

Job Summary

We're looking for an experienced Staff Electrical Safety Engineer to drive our electrical safety and compliance strategy for the Apollo humanoid robot. We are primarily interested in candidates who have developed and released products to the market in robotics, automotive, medical, personal electronics, or enterprise spaces. In this job role, you will own the strategy for requirements, design, and testing for the electrical systems in and around Apollo.

Responsibilities

• Define electrical requirements, design processes, and test strategy to ensure Apollo meets system- and product-level requirements.
• Review system electrical architecture and PCBA designs for safety, compliance, and industry best practices. Ensure proper creepages, clearances, wire sizing, components, and protection methods are followed.
• Develop documentation and perform calculations associated with HARA, DFMEA, MTTFd, FIT, DC, and PFH.
• Collaborate with leadership, program management, and cross-functional teams to plan and execute company strategy.
• Define, simulate, and verify electronics and electrical system requirements.
• Design, implement, and test multi-layer mixed signal PCBAs.
• Design hardware to meet functional safety requirements, implementing redundant systems, fail-safe mechanisms, and diagnostic features to meet or exceed industry safety standards.
• Rapid prototyping of electrical systems at both system and board levels.
• Generate design documentation such as schematics, block diagrams, test plans and procedures, fabrication and assembly drawings.
• Develop and execute comprehensive validation and test plans, design necessary test fixtures, and execute rigorous testing to confirm compliance with performance specifications and regulatory standards (e.g., UL, TÜV).
• Participate in the debugging and root cause analysis related to hardware and software defect resolution.
• Own the entire lifecycle of electronics and electrical systems from initial concept and architecture definition through design, prototyping, validation, production release, change requests, and ongoing support.
• Mentor junior and senior engineers.
• Manage 3rd party relationships with vendors, contract manufacturers, and external design services.

Qualifications

• Bachelors, Masters, or PhD degree (or equivalent) in Electrical Engineering or related field.
• 8+ years of experience in electronics development.
• Demonstrated experience in product safety and compliance including one or more ISO 13849-1, IEC 61508, IEC 60204-1, IEC 61800-5-1, IEC 62368-1.
• Demonstrated experience taking a product through compliance testing with UL/TÜV/etc.
• Experience with mobile robotics standards UL3100, ISO 3961-4.
• Experience designing PCBAs and systems for ESD, hi-pot, creepages and clearances on PCBAs and enclosure.
• Experience debugging electronics and systems with compliance testing fails.
• Competent in CAD tools including Altium or similar tools.
• Extensive experience with electronics lab tools and simulation tools (ex: LTSpice, PSpice).
• Excellent communication (verbal & written); will be expected to develop detailed build assembly instructions and diagrams.
• Excellent problem-solving and hardware debugging skills.
• Hands-on experience with prototyping and testing, including the use of lab equipment.
• Experience with robotics or designing electronics for lightweight, space-constrained systems is a significant plus.
• Nice to have - experience with UL 2271, IEC 62619, or UN38.3.
• Nice to have - subject matter expertise in the following areas: power electronics, motor drive, battery and charger development, high-speed digital or compute carrier board design, or DFx.

PHYSICAL REQUIREMENTS

• Prolonged periods of sitting at a desk and working on a computer 
• Must be able to lift 15 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate 

The Role

Apptronik is seeking a Staff Mechanical Engineer to serve as the technical lead for Apollo’s lower body. This is a high-visibility leadership role responsible for the hip, leg, knee, ankle, and foot assemblies.

You will own the complete lifecycle—architecture, design, integration, and verification—of the lower body stack. This position requires deep expertise in locomotion kinematics, dynamic stability, and high-load structural design. You will lead the development of systems that must deliver human-like mobility, absorb high-energy impacts, and maintain durability across millions of cycles in real-world environments.

Key Responsibilities

System Architecture & Locomotion Design

• Lower Body Ownership: Define the mechanical architecture for the hips, legs, knees, ankles, and feet. Lead trade-off studies between power density, range of motion (ROM), stability, and energy efficiency.
• Locomotion Performance: Architect systems that enable stable walking, running, lifting, and recovery from disturbances (e.g., slips, trips, and falls). Balance dynamic performance with robustness and safety.
• Mass Distribution & Stability: Optimize mass placement and inertia to improve balance, agility, and whole-body coordination.

Complex Mechanism Design

• High-Performance Joints: Drive the design of multi-DOF joints (hip, knee, ankle) capable of high torque output and high cycle life while maintaining precision and backdrivability where needed.
• Shock & Impact Management: Design structures and mechanisms that absorb and dissipate energy during foot-ground contact and high-impact events (e.g., stepping off ledges, falls).
• Structural Integrity: Lead the design of the lower body load path to support full robot mass and dynamic loads using advanced materials and topology optimization.

Ground Interface & Mobility

• Foot & Contact Design: Develop feet and contact interfaces that provide traction, compliance, and adaptability across varied terrains.
• Actuation Integration: Partner closely with controls and actuation teams to ensure mechanical designs support force control, impedance control, and dynamic motion planning.

Integration & Reliability

• Subsystem Integration: Lead integration of actuators, sensors , and structural elements within tight mechanical envelopes.
• Cable & Harness Routing: Architect robust routing strategies through high-flex joints (hips, knees, ankles), ensuring multi-million cycle reliability and maintainability.
• Environmental Robustness: Ensure designs meet requirements for ingress protection (IP), thermal performance, and durability in real-world operating conditions.

Verification & Leadership

• DVT Ownership: Define and execute the Design Verification Test (DVT) plan for the lower body, including fatigue testing, impact testing, and long-duration lifecycle validation.
• Failure Analysis: Lead root cause investigations for field or lab failures related to wear, fatigue, or performance degradation.
• Technical Mentorship: Conduct deep-dive design reviews, establish best practices for dynamic robotic systems, and mentor engineers across experience levels.

Required Skills & Qualifications

• Experience: B.S. in Mechanical Engineering with a 8+ years of experience in mechanical design of complex robotic systems, with a focus on legged systems or high-load dynamic mechanisms.
• Drive Through Influence: Proven ability to lead technical initiatives and align cross-functional stakeholders without direct authority. Strong track record of driving system-level decisions.
• Subject Matter Expertise: Demonstrated experience designing multi-axis robotic legs, exoskeletons, or comparable high-DOF dynamic systems.
• Locomotion & Dynamics: Deep understanding of kinematics, dynamics, and control considerations for legged locomotion.
• Structural & Fatigue Design: Expertise in designing for high-cycle fatigue, impact loading, and durability.
• Packaging Mastery: Strong experience integrating actuators, sensors, and structures in compact, high-performance systems.
• CAD Expertise: Expert-level proficiency in CAD tools (SolidWorks, NX, CATIA).
• Education: BS/MS in Mechanical Engineering, Robotics, or a related field.

Apptronik is seeking a Staff Mechanical Engineer to serve as the technical lead for Apollo’s lower body. This is a high-visibility leadership role responsible for the hip, leg, knee, ankle, and foot assemblies.

You will own the complete lifecycle—architecture, design, integration, and verification—of the lower body stack. This position requires deep expertise in locomotion kinematics, dynamic stability, and high-load structural design. You will lead the development of systems that must deliver human-like mobility, absorb high-energy impacts, and maintain durability across millions of cycles in real-world environments.

Key Responsibilities

System Architecture & Locomotion Design

• Lower Body Ownership: Define the mechanical architecture for the hips, legs, knees, ankles, and feet. Lead trade-off studies between power density, range of motion (ROM), stability, and energy efficiency.
• Locomotion Performance: Architect systems that enable stable walking, running, lifting, and recovery from disturbances (e.g., slips, trips, and falls). Balance dynamic performance with robustness and safety.
• Mass Distribution & Stability: Optimize mass placement and inertia to improve balance, agility, and whole-body coordination.

Complex Mechanism Design

• High-Performance Joints: Drive the design of multi-DOF joints (hip, knee, ankle) capable of high torque output and high cycle life while maintaining precision and backdrivability where needed.
• Shock & Impact Management: Design structures and mechanisms that absorb and dissipate energy during foot-ground contact and high-impact events (e.g., stepping off ledges, falls).
• Structural Integrity: Lead the design of the lower body load path to support full robot mass and dynamic loads using advanced materials and topology optimization.

Ground Interface & Mobility

• Foot & Contact Design: Develop feet and contact interfaces that provide traction, compliance, and adaptability across varied terrains.
• Actuation Integration: Partner closely with controls and actuation teams to ensure mechanical designs support force control, impedance control, and dynamic motion planning.

Integration & Reliability

• Subsystem Integration: Lead integration of actuators, sensors , and structural elements within tight mechanical envelopes.
• Cable & Harness Routing: Architect robust routing strategies through high-flex joints (hips, knees, ankles), ensuring multi-million cycle reliability and maintainability.
• Environmental Robustness: Ensure designs meet requirements for ingress protection (IP), thermal performance, and durability in real-world operating conditions.

Verification & Leadership

• DVT Ownership: Define and execute the Design Verification Test (DVT) plan for the lower body, including fatigue testing, impact testing, and long-duration lifecycle validation.
• Failure Analysis: Lead root cause investigations for field or lab failures related to wear, fatigue, or performance degradation.
• Technical Mentorship: Conduct deep-dive design reviews, establish best practices for dynamic robotic systems, and mentor engineers across experience levels.

Physical Requirements

• Prolonged periods of sitting at a desk and working on a computer 
• Must be able to lift 15 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate