We’re looking for a Principal Engineer to drive the technical direction and architecture of Platform-as-a-Service (PaaS) at DigitalOcean. Our mission is to make deploying, scaling, and managing applications as simple and seamless as possible for developers around the world—from first deploy to internet scale.

As a Principal Engineer on the PaaS team, you’ll play a key role in designing and building the next generation of cloud-native services such as App Platform, Functions, and CI/CD. You’ll architect systems that power our global infrastructure, partner closely with engineering and product teams across the company, and mentor engineers to level up the entire organization. This is a unique opportunity to shape how developers build and ship software on a platform purpose-built for simplicity and scale.

We’re looking for someone who can span technical strategy and hands-on execution—someone who thrives on solving complex distributed problems and multiplying the impact of everyone around them.

What You’ll Do:

• Architect and guide the implementation of high-scale, reliable, and secure systems that underpin our PaaS offerings.
• Drive technical direction and make foundational decisions on system design, scalability, observability, and developer experience.
• Partner with product managers and engineering leadership to define short- and long-term roadmap priorities.
• Identify platform bottlenecks, inefficiencies, and future risks—and design solutions that proactively address them.
• Collaborate across teams to ensure seamless integration between platform services, infrastructure, and developer tools.
• Mentor engineers at all levels and contribute to a culture of technical excellence, inclusivity, and impact.
• Stay ahead of emerging technologies, patterns, and best practices in the PaaS, serverless, and cloud-native ecosystem.

Key Metrics:

• Platform availability and system performance
• Developer adoption and satisfaction
• Technical debt reduction and architectural clarity
• Engineering velocity and cross-team alignment

What You’ll Add to DigitalOcean:

• 11+ years of experience designing and building distributed systems at scale.
• Expertise in one or more backend languages (e.g., Go, Python, C++, Java) and strong fundamentals in systems architecture and infrastructure.
• Proven experience leading the design of large-scale services used by 1000s (or millions) of customers.
• Passion for mentoring and elevating those around you—technical leadership is about multiplying impact.

Compensation Range:

• $227,040 - $283,800

*This is a remote role

JR: 2025-7225

#LI-Remote

#LI-SK1 

About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

Job Summary 

We are seeking an experienced Staff UEFI Engineer to design, develop, and deploy UEFI-based firmware for Graphcore’s hyperscale AI server platforms. 

This role focuses on developing system firmware responsible for platform initialization, hardware configuration, and reliability features across large-scale data center deployments. 

The Team 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

The Firmware Engineering team develops the foundational firmware responsible for platform initialization, hardware configuration, and system reliability across Graphcore’s AI compute infrastructure. 

The team collaborates with silicon engineering, hardware design teams, BMC firmware teams, validation engineers, and platform architects to enable reliable server platform bring-up and operation. 

Responsibilities and Duties 

• Design, develop, and deploy UEFI-based firmware for hyperscale server platforms. 

• Collaborate with ODM partners throughout the design lifecycle from concept to mass production. 

• Integrate UEFI firmware into CI/CD pipelines enabling automated builds, regression testing, and static analysis. 

• Develop firmware functionality supporting platform initialization including CPU, memory, PCIe, and system interconnects. 

• Implement system firmware security features including root of trust, secure boot chains, and signed firmware updates. 

• Develop platform firmware features supporting server reliability, availability, and serviceability (RAS). 

• Build firmware interfaces supporting telemetry, firmware updates, and system management capabilities. 

• Collaborate with hardware, BMC, security, and validation teams to ensure full platform integration. 

• Debug and perform root cause analysis for firmware and hardware issues across lab and production environments. 

Candidate Profile 

Essential 

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. 

• 10+ years of experience developing UEFI or BIOS firmware for server platforms. 

• Strong expertise with UEFI, TianoCore, and firmware architecture design. 

• Experience developing firmware solutions for hyperscale or cloud data center environments. 

• Strong programming skills in C/C++. 

• Deep understanding of DDR memory training, cache coherency protocols, and PCIe subsystems. 

• Strong knowledge of server platform architecture including power delivery, thermal management, sensors, and FRUs. 

• Experience implementing CI/CD pipelines for firmware development. 

• Experience debugging system firmware using logic analyzers, JTAG, GDB, and similar tools. 

Desirable 

• Experience developing UEFI firmware for ARM-based server platforms. 

• Experience with EDK II codebase development and upstream contribution. 

• Experience working with ODM/JDM partners on server platform development programs. 

• Experience delivering firmware for hyperscale cloud deployments and production environments. 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

We are hiring an experienced Security Software Engineer (Staff or Senior) for our Infrastructure Security team to design and build scalable security controls and services within MongoDB Atlas multi-cloud infrastructure.

The team sits within the Site Reliability Engineering organization and works with other engineering teams to ensure that our infrastructure adheres to the highest security standards.

This role can be based out of our New York City, Austin, Seattle or San Francisco offices, or work fully remotely on standard East Coast business hours.

Responsibilities:

• Design and build core security primitives and services that protect MongoDB Atlas compute, networking, and identity across AWS, Azure, and GCP
• Build secure-by-default infrastructure using Linux security mechanisms (AppArmor, SELinux, seccomp, cgroups), Kubernetes, and eBPF to enforce runtime policies and gain deep visibility into systems behaviour
• Develop APIs, automation, and tooling that manage security posture at scale (CSPM, vulnerability management, workload identity) and provide monitoring, logging, and alerting pipelines that integrate with our tooling (Grafana, Splunk, Victoria Metrics.)
• Integrate security into our CI/CD and infrastructure-as-code workflows (Terraform) so that security controls are versioned, reviewed, and deployed just like any other code
• Lead complex projects end‑to‑end, from problem discovery and design docs to implementation, rollout, and long‑term ownership
• Collaborate with SRE, platform and product engineering teams to define secure architectures for new infrastructure and services

Qualifications:

You might be a great fit if you match some of the following:

• 5+ years of experience in Software Engineering, Site Reliability Engineering, or similar roles, preferably with relevant security work
• Proficiency with at least one programming language (Java, Golang, Rust, Python, or C/C++) and experience with infrastructure-as-code tools (Terraform) to automate security configurations and processes
• A deep understanding of Linux and networking concepts, including low-level fundamentals, and how they work together in complex systems
• Experience building security-related features or platforms such as runtime monitoring, CSPM, or vulnerability management
• Experience with a cloud provider (AWS, GCP, or Azure) and their security best practices and building blocks
• Hands-on experience with Kubernetes and its security ecosystem (e.g. RBAC, OPA/Gatekeeper, Kyverno, eBPF, Falco, Tetragon)
• A systems mindset: you think about failure modes, performance, observability, and operability alongside security and correctness
• Strong communication skills and the ability to explain complex security concepts and tradeoffs to both technical and non-technical stakeholders

About MongoDB

MongoDB is built for change, empowering our customers and our people to innovate at the speed of the market. We have redefined the database for the AI era, enabling innovators to create, transform, and disrupt industries with software. MongoDB’s unified database platform—the most widely available, globally distributed database on the market—helps organizations modernize legacy workloads, embrace innovation, and unleash AI. Our cloud-native platform, MongoDB Atlas, is the only globally distributed, multi-cloud database and is available across AWS, Google Cloud, and Microsoft Azure.

With offices worldwide and nearly 60,000 customers—including 75% of the Fortune 100 and AI-native startups—relying on MongoDB for their most important applications, we’re powering the next era of software.

Our compass at MongoDB is our Leadership Commitment, guiding how and why we make decisions, show up for each other, and win. It’s what makes us MongoDB. 

To drive the personal growth and business impact of our employees, we’re committed to developing a supportive and enriching culture for everyone. From employee affinity groups, to fertility assistance and a generous parental leave policy, we value our employees’ wellbeing and want to support them along every step of their professional and personal journeys. Learn more about what it’s like to work at MongoDB, and help us make an impact on the world!

MongoDB is committed to providing any necessary accommodations for individuals with disabilities within our application and interview process. To request an accommodation due to a disability, please inform your recruiter.

MongoDB, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type and makes all hiring decisions without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.

Req ID: 2263171228

We are looking for passionate technologists to join our Pre-Sales organization to ensure that our growth is grounded and guided by strong technical alignment with our platform and the needs of our customers. 

MongoDB Pre-Sales Solution Architects are responsible for guiding our customers and partners to design and build reliable, scalable systems using our data platform. Our team is made up of seasoned software architects and developers who take direct responsibility for customer success, including the design of their software, deployment, and operations. You'll work closely with our field partner leaders and play a key role in winning deals and driving the business forward. You'll be a trusted advisor to a wide range of users from startups to the world's largest enterprise IT organizations.

As an ideal candidate, you will have:

• 8+ years of pre-sales experience with enterprise software and technical aptitude
• Working knowledge and ability to code with one  or more modern scripting languages (e.g. Python, Node.js, SQL) and/or popular programming languages (e.g. C/C++, Java, C#) 
• Experience with scalable and highly available distributed systems 
• 2+ years of software development experience
• Excellent presentation and communication skills 
• The ability to travel up to 50%
• A Bachelor’s degree or equivalent work experience
• Professional proficiency in speaking and writing Portuguese and English 
• Professional proficiency in speaking and writing Spanish is highly preferred

As an ideal candidate, you may also have:

• Experience selling databases and/or deploying applications with any of the major cloud providers 
• Experience with database programming and data modelling
• Knowledge of modern technologies - their function and integration requirements - e.g. Spark, cloud storage/streaming, API mgmt, Kafka, serverless.
• A cloud provider certification
• A MongoDB Certification 

What you do at MongoDB:

• You work with our advisory consulting partners on reference architectures, patterns, and AI blueprints for making the best use of MongoDB 
• You confidently articulate the business value of MongoDB solutions and bridge this to technical value
• You partner with our account teams to help ensure success in accounts ranging from small startups to large enterprises 
• You align to support sales with activities such as technical discovery, demos, proof of value, presentation, sizing, and documentation of technical decision criteria; working across a number of opportunities in parallel
• You translate technical concepts and patterns into business benefits for management and executives 
• You act as a liaison, gathering feedback from the field to relay back to the Product Management team
• You will have the opportunity to help drive demand through participation in both industry-known trade-shows as well account-based marketing events
• You demonstrate resilience and sound judgment in dealing with business challenges
• You have an ability to drive customer demand within a sales territory, by being self-motivated, proactive and understanding the importance of a strong sense of urgency
• You proactively seek opportunities to support and mentor other pre-sales team members and share best practices
• You have situational awareness and react appropriately in group settings

Particularly with Partners:

• You successfully build and maintain effective relationships with technical partners, gaining their trust, influencing their decisions, and reinforcing their understanding of how MongoDB adds value to the broader ecosystem and needs of clients
• You understand the importance of a strong sense of urgency reflected through ability to drive partner demand within the sales territory
• You align to drive partner Center of Excellence strategies and create demand for MongoDB solutions
• You have a strong understanding of partner business model, value, and needs
• You demonstrate the ability to anticipate and respond appropriately to partner objections
• You are seen as a “Trusted Advisor” with technical partner stakeholders
• You team up to build joint proposals with partners for the client
• You drive strategy and implementation of solution architecture for products and services within the partner ecosystem of the region
• You can demonstrate technical expertise of general IT and application operations through mentorship of local partner organizations
• You create strategies that map specific industry trends to account base within local partner organizations
• You create strategies that map competitive threats within local partner organizations

What you will learn:

• The rapidly expanding MongoDB product suite, including:
• Core database server
• Atlas (fully managed cloud database service)
• Atlas Data Lake
• Atlas Full-Text Search
• Realm
• Charts
• Other Tools and connectors - Ops/Cloud Manager, Compass, Connector for BI, Connector for Spark
• Market-relevant, complementary technologies e.g. Apache Kafka, Kubernetes
• Modern and popular architecture design patterns, methodologies and concerns e.g. microservices, event-driven architectures, DevOps, cloud, security
• Sales techniques and related soft skills - presentations, demonstrations, whiteboarding, discovery, objection handling
• Exposure to a wide variety of market verticals and broad spectrum of interesting use cases

About MongoDB

MongoDB is built for change, empowering our customers and our people to innovate at the speed of the market. We have redefined the database for the AI era, enabling innovators to create, transform, and disrupt industries with software. MongoDB’s unified database platform, the most widely available, globally distributed database on the market, helps organizations modernize legacy workloads, embrace innovation, and unleash AI. Our cloud-native platform, MongoDB Atlas, is the only globally distributed, multi-cloud database and is available across AWS, Google Cloud, and Microsoft Azure.

With offices worldwide and over 60,000 customers, including 75% of the Fortune 100 and AI-native startups, relying on MongoDB for their most important applications, we’re powering the next era of software.

Our compass at MongoDB is our Leadership Commitment, guiding how and why we make decisions, show up for each other, and win. It’s what makes us MongoDB. 

To drive the personal growth and business impact of our employees, we’re committed to developing a supportive and enriching culture for everyone. From employee affinity groups, to fertility assistance and a generous parental leave policy, we value our employees’ wellbeing and want to support them along every step of their professional and personal journeys. Learn more about what it’s like to work at MongoDB, and help us make an impact on the world!

MongoDB is committed to providing any necessary accommodations for individuals with disabilities within our application and interview process. To request an accommodation due to a disability, please inform your recruiter.

MongoDB, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type and makes all hiring decisions without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.

REQ ID: 1273379214

JOB SUMMARY

We are seeking an early-career Simulation Engineer to join our growing Simulation team as a generalist contributor. This is an opportunity to learn humanoid simulation across its full breadth — from physics and contact modeling through scene authoring, asset pipelines, and developer tooling — while contributing to multiple ongoing initiatives at once.

You will work across several of the team's focus areas, with near-term emphasis on supporting our dexterous-hand simulation work. As we hire a senior owner for the Dexterity domain, you will help build the foundational infrastructure they will grow into, and over time develop depth in the area where your interests and the team's needs align best.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Dexterity Foundations: Build and maintain hand collision geometry (primitive decomposition, mesh cleanup). Author evaluation scenes and dexterity benchmarks in Isaac Lab / Isaac Sim from specifications. Run sim-to-real comparison experiments and produce comparison reports.
• Design-Time Simulation: Contribute to the CAD-to-simulation pipeline — kinematic graph extraction, collision geometry, mass and inertia property handling. Run design-space exploration experiments per protocols defined by senior team members.
• Robot Description & Asset Pipeline: Help maintain canonical robot models — joint limits, inertias, collision properties. Build and maintain regression tests and validation tooling for the robot assets the rest of the org depends on.
• Production Platform Contributions: Contribute to the simulation platform's tooling, examples, CI infrastructure, and developer documentation. Triage user-reported issues and help unblock other teams using the platform.
• Team Contributions: Own onboarding docs and example scenes that help new engineers get productive on the platform — your perspective as the newest team member is a real asset here.

SKILLS AND REQUIREMENTS:

Must-Have

• 0–2 years of professional software engineering experience (strong internship or research project experience qualifies)
• Strong Python skills
• Solid fundamentals: rigid body dynamics, linear algebra, spatial math, programming
• Coursework or project experience with robotics simulation, computational geometry, or computer graphics
• Demonstrated curiosity and willingness to work across multiple domains rather than specializing immediately

Nice-to-Have

• Hands-on experience with Isaac Sim, MuJoCo, Gazebo, or equivalent simulator (coursework or projects count)
• Familiarity with USD, URDF, MJCF, or other robot/scene description formats
• Exposure to mechanical engineering, robot hardware, or sim-to-real workflows
• Some C++ exposure
• Internship or research experience in robotics, gaming, or graphics

EDUCATION and/or EXPERIENCE:

• BS in Computer Science, Robotics, Mechanical Engineering, or related field. MS welcome but not

PHYSICAL REQUIREMENTS 

• Prolonged periods of sitting at a desk and working on a computer
• Must be able to lift 15 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate

JOB SUMMARY 

We are seeking a Staff Simulation Engineer to be the sole owner of dexterous hand simulation at Apptronik.

This is a high-autonomy, high-impact individual contributor role. You will define how hands are represented in simulation — from contact geometry and physics fidelity all the way through sim-to-real validation — and you will be the authoritative technical voice across Mechanical Design, Controls, and Hardware whenever simulation of the hand is in scope. There is no team beneath you, but your work directly unblocks multiple teams.

Core mandate: make simulation a reliable predictor of physical hand behavior, and own that standard end-to-end.

ESSENTIAL DUTIES AND RESPONSIBILITIES

Contact Dynamics & Physics Fidelity: Own the accuracy of contact simulation for high-DOF robotic hands. Model and tune contact parameters — stiffness, damping, friction, restitution — against real hardware measurements. Develop and maintain hand-specific collision geometry (primitive decomposition, mesh optimization) to ensure simulation contact behavior matches physical interaction.

Sim-to-Real Validation: Design and execute systematic sim-to-real validation workflows. Run side-by-side comparisons of grasping stability, fingertip contact forces, and joint behavior between simulation and hardware. Drive iterative parameter calibration using real sensor data — encoders, F/T sensors, tactile arrays — until simulation predictions are quantifiably reliable

Sensor & Actuator Modeling: Build accurate models of the hand's sensing and actuation systems within simulation — including tactile sensor response, actuator dynamics (compliance, backlash), and encoder noise characteristics.

Evaluation Scene Construction: Design and implement evaluation environments and dexterity benchmarks in Isaac Lab / Isaac Sim. Own the physical property modeling — contact materials, object mass/inertia, surface textures — required for high-fidelity task simulation.

Asset Pipeline: Contribute to CAD-to-USD conversion workflows as needed — collision mesh generation, joint limit extraction, kinematic parameter import. This is infrastructure support, not a primary focus.

SKILLS AND REQUIREMENTS

Must-Have

• 4+ years of hands-on robotic simulation experience (Senior); 7+ years (Staff)
• Experience with robotic hands or high-DOF manipulators
• Demonstrated experience with contact-rich simulation — not just kinematics and trajectory playback
• Experience with physics parameter identification (sysid) or domain randomization pipelines
• Proven ability to operate as a domain owner: setting technical direction, making independent architectural decisions, and driving cross-functional alignment through expertise
• Strong Python skills; C++ a plus
• Solid fundamentals: rigid body dynamics, contact mechanics, collision geometry, spatial math
• Hardware-grounded: experience running sim-to-real comparisons with real sensor data

Nice-to-Have

• Deep working knowledge of Isaac Sim, MuJoCo, or equivalent modern robotics simulator
• Familiarity with tactile sensing or F/T sensor integration in simulation
• USD proficiency: composition arcs, layers, stages
• Background in teleoperation or motion retargeting

EDUCATION and/or EXPERIENCE 

• MS or PhD in Robotics, Computer Science, Mechanical Engineering, or related fields.

PHYSICAL REQUIREMENTS 

Prolonged periods of sitting at a desk and working on a computer
Must be able to lift 15 pounds at times
Vision to read printed materials and a computer screen
Hearing and speech to communicate

Team Description:

The Surgery & Robotics Hardware Team is looking for Electrical Engineers who want to advance the future of healthcare solutions with technology. At Neuralink we recognize that increasing healthcare costs, lack of access, and insufficient numbers of neurosurgeons globally require new approaches to enable greater access to our devices. To address these challenges we design fully autonomous robotics systems, human assistive surgical tools, and design entire surgical suites in order to provide better experiences for our customers.

Our team works on our surgical robot system which aims to fully automate the implantation of the Neuralink implant. We design and integrate multi-axis robotic arms, perception systems including custom imaging hardware, optical coherence tomography tissue imaging, power electronics, and safety systems such as 3D spatial mapping/object avoidance sensors. Robotics is part of a larger system of tools we work on. For example, using pre-op MRI scans we generate patient anatomy data that we later use in surgery to register precise surgery site locations. 

In addition to research and development of modern surgical technology, we also are responsible for bringing these technologies to market. We perform full lifecycle testing for all devices we design and ultimately manufacture them for use in human surgeries. To date, our designs have served over 20 individuals, and in the coming years our designs will serve thousands of individuals who wish to use our implant technology.

Job Description and Responsibilities:

As an Electrical Engineer on the Surgery & Robot Hardware Team, you will be expected to design, verify, and oversee the transition to production of a variety of custom electronics systems.  This role offers substantial autonomy and the exciting opportunity to own creative decisions and execute on new, impactful projects such as robotics stage designs, motor drives and controls, custom camera designs, manufacturing automation, and the firmware that enables all of these devices.

Required Qualifications: 

• Bachelor’s degree in Electrical Engineering or a related field or equivalent experience
• Professional experience delivering on all phases of electronics design (requirements, part selection, schematic, layout, manufacturing, test)
• Demonstrated depth in at least one of the following:
  • Power electronics: experience designing custom power conversion, distribution, eFusing, and battery management systems in the low-to-medium (1W-2kW) range
  • FPGA hardware design for time sensitive systems such as image processing, high-speed data acquisition, or real time networking. Professional experience in FPGA selection, RTL development, digital signal processing theory and techniques, and hardware design to interface high speed physical layer devices via PCIe, MIPI, SLVS-ec, LVDS, etc
  • Manufacturing automation design: professional experience architecting and implementing manufacturing automation solutions for products that currently ship at the scale of 1000’s+
• Practical electronics design knowledge including designing for EMC, ESD, thermals and packaging

Preferred Qualifications: 

• A portfolio showcasing your hardware designs 
• Demonstrable experience developing electronics for safety critical systems such as medical devices, aerospace, automotive, or military
• Demonstrable experience shipping code in one of the following languages: C, C++, Python, or Rust
• Altium experience

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As a Digital IC Design Engineer Intern, your responsibilities will include:

• Micro-architecture design and RTL implementation of: 
• Low-power digital signal processors
• Low-power general-purpose hardware accelerators
• Low-power graphics processing units
• Low-power radio MAC/PHY
• Low-power serial link MAC/PHY
• Design and implementation of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
• Complex system modeling for energy and performance benchmarks
• Workload analysis and modeling
• Leveraging architecture-level design trade-offs with process technology and workload type
• Balancing energy efficiency and performance under manufacturing process variation 
• Complex system-on-chip verification
• Behavioral level modeling and model equivalence check
• FPGA emulation
• Analog mixed-signal co-simulation
• Design for testability 
• Collaboration on silicon bring-up tests with silicon validation engineers 

Required Qualifications:

• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• 2+ years of experience in digital design
• Proficient in SystemVerilog, C/C++, Python
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications:

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++, or UVM 
• Experience automating tool flows
• Experience with embedded design
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization
• Experience designing PCBs or writing firmware.

Expected Compensation:

The anticipated hourly rate for this position is listed below.

California Hourly Flat Rate:
$35/Hr USD

Team Description:

At Neuralink, we're engineering the future of automated surgeries, focusing on the safe and effective implantation of our groundbreaking Neuralink implant. Our team — a cross-functional mix of roboticists, engineers from various disciplines, and medical professionals — collaborates on developing a surgical flow from first principles. In this critical role, you'll straddle the cutting-edge worlds of robotics, software, and neuroscience.

Job Description and Responsibilities:

This is a new and foundational role for our team that will allow you to create new embedded systems from scratch while challenging and refining the old. As a Firmware Engineer, your responsibilities will encompass:

• Developing and optimizing embedded software for robotic surgery applications
• Streamlining our codebase by refining and, when necessary, retiring legacy embedded software
• Rigorous testing and validation of software systems to meet the highest safety and reliability standards
• Participating in peer code reviews
• Writing drivers and applications to extend the functionality of our robotics
• Specifying hardware and software choices as we develop future hardware platforms
• Sharing your findings and progress with the team in a collaborative environment

Required Qualifications:

• Demonstrated track record of success in a science or engineering field, evidenced by outstanding projects, innovations, or advanced problem-solving
• Proven experience in software development, preferably with exposure to embedded systems

Preferred Qualifications:

Embedded Software Development:

• 2+ years of experience with embedded systems
• Proficient with common communication protocols (SPI, UART, I2C, etc.)
• Comfortable/working knowledge of more advanced protocols such as PCIe, MIPI CSI/DSI, USB, and 802.3
• Proficient in at least one embedded language such as C, C++, or Rust
• Proficient with embedded toolchains and workflow
• Experience building and bringing-up MCUs or FPGAs
• Experience with embedded stacks for ARM cores
• Experience developing on embedded Linux platforms
• Experience with embedded Linux kernel configuration and device tree setup
• Experience with kernel driver development
• Experience with ARM bootloaders
• Experience coding drivers for actuators and sensors
• Experience with high speed data acquisition and processing

Electrical Engineering:

• Foundational understanding of MCU architectures and peripheral integration
• Solid knowledge in electrical engineering and DSP
• Ability to interpret electrical schematics and datasheets, along with proficiency in using lab equipment

Team Description: 

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Description & Responsibilities: 

Our Hardware/ Software Co-Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.

• Micro-architecture design and RTL implementation of: 
• Low-power digital signal processors
• Low-power general-purpose hardware accelerators
• Low-power graphics processing units
• Low-power radio MAC/PHY
• Low-power serial link MAC/PHY
• Design and optimization of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
• Complex system modeling for energy and performance benchmarks
• Workload analysis and modeling
• Energy/performance profiling and analysis
• Leveraging architecture-level design trade-offs with process technology and workload type
• Balancing cost and performance under manufacturing process variation 
• Collaboration on silicon bring-up tests with verification engineers 

Required Qualifications:

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• Experience designing and implementing embedded software in C or Rust
• Expertise in SystemVerilog, C/C++, Python
• Experience designing and implementing  emulation models, transactors, and test environments to replicate hardware behavior
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications: 

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
• Experience automating tool flows
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization

Team Description:

The Robot Software Team builds software that enables scalable neurosurgery that allows safe implantation of the N1 device, ranging from core control, sensors and perception, autonomy, surgery analytics, and more. This role tightly integrates with the robot hardware team, surgery engineering team, as well as the BCI applications team which rely on us to deliver safe and effective implantation of the N1 device. 

Neuralink strives to be a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us.

Job Description and Responsibilities:

As a Software Engineer Intern on the Robot Software Team, you will be responsible for writing software and making sure your code works on an actual surgical robot, not just simulation. Our robotics integrate actuated devices with microelectromechanical systems as well as novel surgical procedures. These applications place strong emphasis on high-precision, high-repeatability mechanical motion, as well as high reliability and fail-safe design. You will be expected to:

• Develop safety-critical software for the robot; you are responsible for contributing directly to surgery-ready software as an intern
• Take ownership of a project that is integral to robot functioning from design to implementation under the guidance of a robot software team member
• Jump on problems when they arise with a strong bias for action to support robot operation by non-software teams
• Work across different engineering disciplines; your software may involve interactions with the mechanical, electrical, biological, and neuroscience teams

Required Qualifications: 

• Evidence of exceptional ability in engineering or computer science
• Experience in writing performant applications in a system language like C, C++, and Rust
• Ability to work on mission-critical and safety-critical systems
• Strong bias for action and first principles thinking

Preferred Qualifications: 

• Hands-on experience with robotics or high-reliability systems
• Experience coding in Linux and debugging on Linux systems
• Experience in computer vision
• Experience in kinematics and motion planning
• Experience working on medical robots
• Experience working in a high-precision environment

Pay Transparency:

Based on California law, the following details are for California individuals only:

California Hourly Rate:

$35/hr USD

Team Description: 

The Infrastructure Team builds the foundation that enables the company to operate safely, robustly, and move at light-speed. We run a mixture of cloud-based and on-prem systems and have a user base spanning from highly technically proficient engineers to non-technical scientists and doctors; but all of them need solid systems, rugged networking, and bullet-proof software to do their jobs. This role will integrate tightly with teams across the company, and span all layers of the work environment stack, from deployment of physical hardware on the manufacturing line, to custom tooling to stream neural recordings from implants.

Tech Stack:

• Rust, Python
• Terraform
• Bazel and Nix
• Kubernetes
• GitLab CI
• AWS
• Ubuntu, Fedora

Focus:

• Developing the foundations for teams to build the software and systems required for record-breaking BCI experiences.
• Enhancing developer experience with robust tooling and build-system infrastructure.
• Building foundational infrastructure for HITL (hardware in the loop) testing across firmware, BCI, and robot teams.
• Ground-up infrastructure of on-premise solutions as well as cloud architecture.
• Foundational software engineering with a focus on serving internal software teams.

Qualifications: 

• Experience using IAC tools such as Terraform, Docker, Packer, Ansible, Cloud-Init, Kickstart.
• Working knowledge of compiled languages, ideally Rust, Go, or C/C++.
• Working knowledge of major cryptographic protocols and authentication schemes such as TLS, x509, 802.1x, U2F, SAML.
• Familiarity with modern Linux boot process, UEFI, TPM measured boot, Secure Boot, Systemd.
• Systems administration experience on Windows, macOS, and Linux.
• In-depth understanding of modern networking and common protocols.
• Ability to architect, build, and ship 0 to 1 infrastructure quickly and efficiently.

Team Description:

We build the electrical systems that make high-bandwidth brain–computer interfaces possible. This includes neural signal acquisition and stimulation to wireless power delivery, embedded processing, and system integration—all within devices small enough to be implanted in the human body and efficient enough to operate under strict thermal and power constraints. Our work sits at the intersection of analog, RF, digital, and biological systems. Many problems in this space do not present clean abstractions or clear failure modes. Success often depends on careful measurement, iteration, and engineering judgment across multiple interacting systems.

Job Description and Responsibilities:

We are looking for an experienced, hands-on electrical engineer for implant electronics board design, integration with our custom chips, testing, and quality control. You will have the opportunity to contribute to advanced projects, not only work on incremental changes, and be an integral member of a small, fast-moving team. You will be working on all phases of board design (part selection, schematic design, layout, and bring-up) as well as collaborating closely with chip designers, firmware engineers, mechanical engineers, and microfabrication experts for system integration.

• Utilize electrical engineering fundamentals and best system design practices to build on your ability to deliver high-performant, reliable, and manufacturable extremely size-constraint systems
• Gain understanding of all phases of system and board design, from system definition to part selection, schematic design, layout, bring up, and design verification
• Contribute to R&D investigations and experiments to demonstrate feasibility of new technology for the implant and the charger
• Gain experience working cross functionally to ensure successful systems integration
• Contribute to system improvements that decrease latency and increase battery life, reliability, and safety
• Develop ability to design and deploy systems for implant-charger hardware in the loop testing, and manufacturing line quality control

Required Qualifications: 

• Strong EE fundamentals
• Experience designing PCBs for low power and size constrained applications
• Experience with PCB CAD tools (Altium, Eagle, KiCad, Allegro)
• Experience with sensors, power management, and signal/power integrity
• Comfortable with common communication protocols (SPI, UART, I2C, etc.)
• Comfortable with lab equipment (oscilloscope, VNA, etc.)
• Basic C and Python programming skills

Preferred Qualifications:

• Experience with firmware development for embedded systems (C/C++)
• Experience with wireless systems (BLE, WIFI, Zigbee)
• Experience building and bringing-up MCUs or FPGA
• Proficiency with ME CAD tools (Solidworks, AutoCAD)
• Experience with analog circuit design

Expected Compensation:

The anticipated hourly rate for this position is listed below.

California Hourly Flat Rate:
$35/Hr USD

Team Description: 

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Description & Responsibilities: 

Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.

• Micro-architecture design and RTL implementation of: 
• Low-power digital signal processors
• Low-power general-purpose hardware accelerators
• Low-power graphics processing units
• Low-power radio MAC/PHY
• Low-power serial link MAC/PHY
• Design and optimization of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
• Complex system modeling for energy and performance benchmarks
• Workload analysis and modeling
• Energy/performance profiling and analysis
• Leveraging architecture-level design trade-offs with process technology and workload type
• Balancing cost and performance under manufacturing process variation 
• Collaboration on silicon bring-up tests with verification engineers 

Required Qualifications:

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• 5+ years of experience in digital design
• Expertise in SystemVerilog, C/C++, Python
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications: 

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
• Experience automating tool flows
• Experience with embedded design
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization

Team Description:

Join the Brain Interfaces Software Team and be part of a team of remarkable and driven engineers accelerating our pathway to human ready brain-computer interfaces. We are a small, but fast-moving team that collaborates with other exceptional teams of mechanical, electrical, and firmware engineers.

Neuralink strives to be, as much as possible, a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us.

Job Description & Responsibilities:

We are looking for a versatile Software Engineer who is passionate about architecting and implementing elegant software solutions and thrives with autonomy to propose creative approaches to problems. You will be responsible for writing software to interact with Neuralink’s implant, as well as building systems for manufacturing and testing the device. Additionally, you will be expected to:

• Develop and improve Neuralink’s implant manufacturing line acceptance software and station
• Develop and improve Neuralink's implant design verification testing software
• Optimize and maintain Neuralink’s implant software build infrastructure
• Develop and improve Neuralink’s implant SDK

Required Qualifications:

• Fluent in Python and at least one system language including Rust, C++, and C (don’t get hung up on this—being an exceptional software engineer matters above all)
• Experience and proficiency with Linux/Unix systems
• Evidence of exceptional ability in engineering, mathematics, or computer science
• Solid understanding of engineering first principles
• Strong intuition for what matters in a production system vs. research-grade environments

Additional Requirements and Competencies:

• You find large challenges exciting and enjoy discovering and defining problems as much as solving them
• You deliver; you may enjoy thoughtful conversations about problems and perfecting design, but in the end, you know that what matters is delivering reliable solutions (Our ultimate aim is to help people; the “right” solution doesn’t always achieve that)
• You are mission-driven and goal-oriented in your approach to solving problems
• You feel a sense of urgency to get things done sooner rather than later—because there is so much we, as people, can contribute to the world and accomplish in this life, it’s a shame to waste time
• You are resourceful, flexible, and adaptable; no task is too big or too small

ICON is looking for a Senior Robotics Software Engineer to join our Software team in Austin, TX. As a Senior Robotics Software Engineer, you will help develop and maintain robotic control software for all of ICON’s robotic systems. You will be responsible for developing high-performance C++ software to drive complex arm motions, integrating real-time sensor data, and ensuring reliable motion planning. This role is based at ICON’s Austin, TX headquarters, and will report to the Director of Embedded Software Engineering.

RESPONSIBILITIES

• Design, develop, and optimize high-performance C++ software for controlling and coordinating large-scale robotic arms.
• Develop robust motion planning and trajectory generation algorithms to safely navigate industrial arms through complex workspaces.
• Implement real-time sensor fusion and state estimation algorithms (using sensors like IMUs, LiDAR, etc.) to improve arm localization and end-effector precision.
• Program robotic arm motions in coordination with other systems.
• Develop and maintain simulated environments and automated test frameworks to support continuous integration and system verification.
• Lead system integration and validation efforts across hardware and software.
• Participate in architecture decisions for controls and electrical systems, including component selection and standardization.
• Participate in design & code reviews to maintain consistency and high-quality output.

MINIMUM QUALIFICATIONS

• Masters Degree or higher in Software Engineering, Robotics, Mechanical Engineering, or a related field.
• 5+ years of professional experience in robotics software development.
• Expert-level proficiency in modern C++ (17 or newer) and Python within a professional robotics software development environment.
• Deep foundational understanding of robotic arm kinematics (forward and inverse), multi-body dynamics, and motion planning.
• Hands-on experience with robotic platforms, sensors, actuators, localization, perception, and control systems.
• Practical experience designing and optimizing sensor fusion and state estimation algorithms (e.g., Kalman Filters).
• Strong knowledge of autonomy algorithms, robotics frameworks (such as ROS), and simulation environments.

PREFERRED QUALIFICATIONS

• Experience programming industrial robots in high-level languages.
• Experience in formal control theory and linear algebra.
• A general understanding of how to manage redundant kinematic chains or stabilize dynamic systems.
• Proven track record of delivering products to end users and production environments.
• Familiarity with hardware design, prototyping, and manufacturing processes.
• Excellent problem-solving skills and a strong analytical mindset to identify issues, propose innovative solutions, and make data-driven decisions.
• Ability to earn trust, maintain positive and professional relationships, and contribute to a culture of performance.

Senior Post Silicon Validation Engineer (Bringup)

Salary $156,500 - $211,700 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

Job Summary 

We are seeking an experienced Principal Hardware Diagnostics Engineer to design and develop diagnostics software used to monitor hardware health and diagnose system-level issues across Graphcore’s AI infrastructure platforms. 

This role focuses on building diagnostics agents, tools, and analytics frameworks that enable engineers and automation systems to identify, isolate, and resolve hardware issues across blade-level servers and rack-scale clusters. 

The Team 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.    

The Systems Engineering and Platform Validation team ensures Graphcore’s AI compute platforms are reliable, diagnosable, and operationally robust at scale. 

The team collaborates with hardware engineering, firmware, cloud infrastructure, and automation teams to develop tools and frameworks that monitor system health, detect hardware failures, and accelerate root-cause analysis across AI clusters. 

Responsibilities and Duties 

• Design and develop automated hardware diagnostics solutions for blade-level servers and rack-scale AI systems. 

• Architect and implement diagnostic agents, monitoring tools, and analytics frameworks to track hardware telemetry. 

• Collaborate with hardware teams to integrate low-level diagnostic modules into monitoring systems. 

• Develop diagnostics tools capable of detecting hardware health conditions and isolating failures. 

• Create diagnostic modules used for internal validation and production data center operations. 

• Provide detailed hardware fault information to system engineers to accelerate troubleshooting. 

• Define remediation workflows and insights for hardware fault scenarios across nodes and clusters. 

• Collaborate with firmware, networking, and cloud platform teams to integrate diagnostics across the system stack. 

Candidate Profile 

Essential 

• Bachelor’s, Master’s, or PhD in Computer Science, Computer Engineering, or related discipline. 

• Strong software engineering experience in Python, C++, or C#. 

• Experience developing diagnostics or monitoring systems for hardware platforms. 

• Experience working with distributed systems or cloud infrastructure. 

• Strong knowledge of Linux environments and system-level diagnostics tools. 

• Experience collaborating with CM/ODM partners on manufacturing diagnostics and fault isolation. 

• Strong analytical and debugging skills. 

• Excellent communication and collaboration abilities. 

Desirable 

• Experience working with AI hardware platforms or accelerator-based computing systems. 

• Familiarity with hyperscale data center infrastructure. 

• Experience building cluster-level monitoring or diagnostics systems. 

• Experience interacting with internal or external customers during diagnostics solution development. 

About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

Job Summary 

We are seeking an experienced Principal Security Firmware Engineer to design, implement, and validate security mechanisms within embedded firmware and low-level system software supporting Graphcore’s AI compute platforms. 

This role focuses on protecting hardware platforms through secure firmware architecture, trusted boot mechanisms, and secure firmware update frameworks while working closely with hardware, firmware, and security architecture teams. 

The Team 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

The Firmware and Platform Security team is responsible for securing Graphcore’s AI infrastructure platforms across firmware and hardware interface layers. 

The team collaborates with silicon engineering, hardware design teams, firmware developers, and security architects to implement trusted boot chains, secure firmware update mechanisms, and hardware-rooted security capabilities. 

Responsibilities and Duties 

• Design and implement secure firmware architectures for embedded and hardware systems. 

• Develop secure boot, firmware authentication, hardware root of trust, and secure firmware update mechanisms. 

• Define threat models and security requirements for firmware components. 

• Develop and maintain secure embedded firmware using languages such as C, C++, and Rust. 

• Integrate cryptographic libraries and hardware security modules (HSM/TPM). 

• Implement protections against firmware tampering, side-channel attacks, fault injection, and reverse engineering. 

• Perform firmware security assessments, code reviews, and vulnerability analysis. 

• Conduct penetration testing, fuzz testing, and other security validation techniques. 

• Collaborate with hardware teams to integrate chip-level security features. 

• Ensure firmware implementations align with industry standards such as NIST, FIPS, and Secure Development Lifecycle practices. 

Candidate Profile 

Essential 

• Bachelor’s or Master’s degree in Computer Engineering, Computer Science, Electrical Engineering, or related discipline. 

• 5–10+ years of experience in embedded systems or firmware development. 

• Strong programming experience in C and C++. 

• Deep understanding of secure boot architectures and trusted boot chains. 

• Strong knowledge of cryptographic protocols and secure firmware design practices. 

• Experience working with embedded operating systems such as FreeRTOS, Zephyr, or Linux. 

• Experience implementing secure firmware update systems and cryptographic key management. 

Desirable 

• Programming experience in Rust. 

• Experience integrating TPM or hardware security modules (HSM). 

• Experience with static analysis and security tools such as Coverity. 

• Knowledge of secure silicon architectures and trusted execution environments. 

• Experience contributing to open-source firmware security projects. 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Principal Embedded SW/FW Engineer (Bringup)

Salary $241,100 - $326,100 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Senior Embedded SW/FW Engineer (Bringup)

Salary $156,500 - $211,700 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Principal Post Silicon Validation Engineer (Bringup)

Salary $241,100 - $326,100 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Our team has built a high-performance RISC-V CPU from the ground up and is committed to building the best AI platform possible. We value collaboration, curiosity, and a passion for solving hard technical problems across software, compute, networking, and semiconductors.

As part of the Platform Architecture team, the Data Movement Architecture Intern will help shape the performance of our next-generation AI, CPU, and heterogeneous platforms. You’ll work closely with architects and software engineers to design, model, and analyze how data movement subsystems impact system behavior and application-level performance.

This role is remote, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO.

Who You Are

• A highly motivated student who enjoys deep technical exploration and performance analysis.
• Curious about how data moves across compute, memory, and networking in complex AI/CPU systems.
• Comfortable interpreting simulation data and evaluating architecture tradeoffs.
• A strong communicator who collaborates well across multidisciplinary teams.

What We Need

• Pursuing an MS/PhD in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
• Solid understanding of computer architecture topics such as interconnects, memory hierarchies, and caching.
• Proficiency in C/C++ and scripting languages like Python or Shell.
• Experience with RTL design and simulation.

What You Will Learn

• Designing and optimizing data movement subsystems including CPU controllers, DMA engines, and accelerators.
• Conducting performance exploration for CPU controller features and system-level data movement.
• Performing PPA analysis and developing reduced data movement kernels for modeling and emulation.
• Working with software, RTL, and architecture teams to understand real-world AI/CPU workloads.

In this role, you will learn Functional verification of high-performance CPUs going into industry leading AI/ML architecture. You will be mentored by and work alongside a group of highly experienced engineers across various domains of the AI chip.

This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.

This is for our Fall 2026 Semester

Join the team building high-performance RISC-V CPU cores at Tenstorrent. As a Performance Verification Intern, you will work alongside CPU architects, micro-architects, and performance engineers to ensure our designs meet real-world performance demands. This is a hands-on role that spans simulation, emulation, debug, and analysis.

This role is on-site, full-time (40 hours/week) in Santa Clara, CA or Austin, TX.

Who You Are

• Pursuing a BS, MS, or PhD in EE, ECE, CE, or CS with strong academic performance.
• Experienced with assembly, C/C++, and scripting in Python or Perl.
• Familiar with CPU architecture and performance concepts, including pipelines, memory systems, and branch prediction.
• Comfortable working through complex debug problems in a methodical, detail-oriented way.
  
  

What We Need

• Interns who can create performance test plans and write stimulus to stress real CPU scenarios.
• Engineers who can run simulations and emulations to validate performance metrics.
• Contributors who can bring up and debug workloads ranging from open-source benchmarks to industry-standard suites.
• Teammates who can investigate mismatches between RTL and performance models and help root-cause bottlenecks.
  
  

What You Will Learn

• How CPU performance is measured, validated, and optimized before silicon.
• How performance models, RTL implementations, and debug tools come together in a real chip development workflow.
• Techniques for balancing tradeoffs in microarchitecture to hit performance targets.
• What it takes to collaborate across architecture, design, and post-silicon teams in a high-performance CPU project.

At Tenstorrent, you will have the chance to accelerate your career by working on challenging engineering problems with a dedicated mentor and the opportunity to move between the digital design, verification, firmware, software and system engineering teams.   

This role is hybrid based in Austin, TX

Responsibilities:

• Develop machine learning graph compiler 
• Participate in the co-design of Tenstorrent's hardware and software stack 
• Benchmark, analyze, and optimize performance of key machine learning applications across Tenstorrent's hardware and software stack 
• Develop performance analysis and estimation infrastructure that feeds into Tenstorrent compiler 
• Develop high-performance run-time engine 
• Integrate the Tenstorrent software into leading machine learning frameworks 
• Work closely with machine learning engineers to discover the hardware and software requirements of current and future machine learning applications 
• Develop novel ML models and primitives that take advantage of Tenstorrent’s breakthrough architecture to deliver orders of magnitude performance & efficiency improvements 

Experience & Qualifications:

• Final year BS/MS or PhD candidate in EE/ECE/CE/CS with a strong GPA
• Experience with algorithms, data structures, and software development in C/C++. Python expertise is welcome as well 
• Familiarity with and passion for any of the following -- machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture -- is a plus 
• Strong problem solving and analytical skills

As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.

Who You Are

What We Need

• Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.
• Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.
• Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.
• Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.

What You Will Learn

• How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.
• Practical experience in extending existing ML systems and implementing cutting-edge algorithms.
• Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.
• Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.

This role entails design and development of scalable infrastructure and software for the verification of high performance CPUs going into industry leading AI/ML architecture. The successful candidate will be responsible for development and automation of many aspects of the verification environment. The person coming into this role will have opportunities such as: writing low-level RISC-V assembly, building complex low-latency multithreaded testbenches, database programming, software testing and release automation, verilog coding and optimization of CPU components, and contributing to open source projects in the RISC-V ecosystem.

This role is on site, based out of Santa Clara, CA or Austin, TX.

This is for our Fall 2026 Semester

Responsibilities:

• Build software and scripts for high performance simulation and emulation of CPUs
• Improve verilog for optimal simulation performance and fpga emulation synthesis
• Maintain and enhance the Git infrastructure to support CI/CD, nightly regressions across multiple development platforms
• Build software tools and scripts for design flow automation

Experience & Qualifications:

• Currently working towards a Bachelors program
• Strong programming skills. C++, Python, SystemVerilog preferred.
• Solid experience with the Linux operating system
• Experience with version control. Git preferred.
• Interest in CPUs, hardware design, and/or programming
• Willing to learn and adapt

As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is on-site, hybrid, based out of Santa Clara, CA working 4 days in office, 1 day remote. 

Who You Are

What We Need

• Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.
• Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.
• Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.
• Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.

What You Will Learn

• How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.
• Practical experience in extending existing ML systems and implementing cutting-edge algorithms.
• Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.
• Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.

At Tenstorrent, you will have the chance to accelerate your career by working on challenging engineering problems with a dedicated mentor and the opportunity to move between the digital design, verification, firmware, software and system engineering teams.   

This role is on-site based in Austin, TX; Santa Clara, CA; or Toronto, ON

Responsibilities:

• Develop machine learning graph compiler 
• Participate in the co-design of Tenstorrent's hardware and software stack 
• Benchmark, analyze, and optimize performance of key machine learning applications across Tenstorrent's hardware and software stack 
• Develop performance analysis and estimation infrastructure that feeds into Tenstorrent compiler 
• Develop high-performance run-time engine 
• Integrate the Tenstorrent software into leading machine learning frameworks 
• Work closely with machine learning engineers to discover the hardware and software requirements of current and future machine learning applications 
• Develop novel ML models and primitives that take advantage of Tenstorrent’s breakthrough architecture to deliver orders of magnitude performance & efficiency improvements 

Experience & Qualifications:

• Final year BS/MS or PhD candidate in EE/ECE/CE/CS with a strong GPA
• Experience with algorithms, data structures, and software development in C/C++. Python expertise is welcome as well 
• Familiarity with and passion for any of the following -- machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture -- is a plus 
• Strong problem solving and analytical skills

Join the team revolutionizing AI computing at Tenstorrent. You'll work on TT-Forge, our MLIR-based compiler that enables developers to run AI on all configurations of Tenstorrent hardware using an open-source, performant, and general-purpose compiler. You will be at the forefront of the AI hardware revolution, building compiler technologies that redefine what’s possible.

 This role is hybrid, and can be based out of Santa Clara, CA; Austin, TX; or Toronto; ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A passionate software engineer eager to work on compiler technologies and the challenges of AI hardware, whether from compilers, systems, or broader software backgrounds.
• Fluent in C++ and Python, with experience building complex systems that bridge high-level frameworks to low-level execution.
• Excited by compiler optimization and machine learning, with experience in PyTorch, JAX, TensorFlow, or deep systems programming.
• A collaborative problem-solver who thrives in open-source and enjoys working closely with hardware and software engineers.

What We Need

• A drive to solve novel challenges in AI compilation, from optimizing computational graphs to creating custom dialects and transformation passes.
• Experience or strong interest in MLIR and how modular compiler frameworks connect AI models to advanced hardware.
• Motivation to build technology that impacts the future of AI, knowing your work will enable the next wave of breakthroughs.

What You Will Learn

• How to build open-source compiler frameworks supporting diverse AI models and workloads, including training and multi-chip scaling.
• Deep expertise in compiler technologies including custom MLIR dialects (TTIR, TTNN, TTKernel) and transformation passes.
• New methods for human-in-the-loop compiler optimization using TT-Explorer, making advanced tuning tools usable by all developers.
• How compiler technology powers Tenstorrent’s mission to deliver affordable, open-source AI computing in a highly competitive space.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

• Experienced compiler engineer with deep knowledge of GCC and LLVM internals, comfortable optimizing for custom hardware targets.
• Strong C/C++ developer with a solid grasp of algorithms, data structures, and performance analysis.
• Collaborative and analytical, able to work across hardware and software domains to deliver efficient, high-performance toolchains.
• Passionate about enabling breakthrough compute architectures through compiler innovation and software-hardware co-design.

• Design, develop, and optimize GCC and/or LLVM compilers for Tenstorrent’s custom RISC-V hardware and AI vector engines.
• Contribute to the co-design of Tenstorrent’s hardware and software stack to maximize performance and programmability.
• Benchmark, analyze, and tune performance of core applications across RISC-V and AI software environments.
• Collaborate with ML engineers to identify and implement compiler support for emerging AI workloads and frameworks.

• How compiler design directly impacts the performance and efficiency of next-generation RISC-V and AI architectures.
• Advanced techniques in hardware-software co-optimization and compiler-driven performance tuning.
• Integration of custom compilers with leading ML frameworks and runtime environments.
• The end-to-end toolchain flow that enables Tenstorrent’s scalable, high-performance AI compute systems.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are seeking a junior-to-mid level SOC Emulation Engineer to support our hardware emulation infrastructure and internal chip design teams. This role focuses on integrating vendor and custom hardware transactors, developing Python-based test frameworks, and providing technical support to emulation users across multiple chip projects.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Background in Electrical/Computer Engineering or Computer Science with 1-3 years of experience in chip design, verification, or emulation.
• Proficient in Python for automation and test development, with a working knowledge of C++ and the ability to navigate SystemVerilog RTL.
• Skilled at using modern AI tools (Claude, ChatGPT, Copilot) to accelerate code generation, debugging, and documentation analysis.
• Energetic about supporting diverse teams, from high-level software to low-level firmware, to solve complex runtime and build issues.

What We Need

• Ability to integrate vendor and custom transactors into RTL testbenches while handling clock domain and tri-state resolution.
• Experience building Python APIs (using pybind11) and maintaining CMake-based compilation flows for emulation libraries.
• Solid understanding of standard chip interfaces, bus protocols, and hardware synchronization (resets/clocking).
• A commitment to triaging and debugging the full stack, spanning from Python tests and C++ bindings down to hardware.

What You Will Learn

• Deepening your expertise with world-class platforms like Synopsys Zebu for massive-scale silicon validation.
• Gaining a holistic view of chip development by bridging the gap between hardware RTL and software drivers.
• Building and optimizing large-scale emulation build and run tooling for high-performance engineering teams.
• Refining your ability to gather requirements and facilitate communication between hardware designers and software engineers.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

• Leadership to drive compiler development across multiple layers of the stack, including custom dialects, transformation passes, and runtime integration.
• Alignment with hardware, software, and ML teams to ensure the compiler supports realistic performance and deployment needs.
• Technical ownership of roadmap priorities, planning, and mentorship for a high-performing engineering team.
• Insight to identify bottlenecks, debug performance issues, and improve developer workflows across the stack.

• Experience building compilers or similar systems, with strong fluency in C++ and Python.
• Strong knoweledge of MLIR, LLVM, or related infrastructure, with hands-on work in dialect design or optimization passes.
• You have a strong understanding of modern AI frameworks like PyTorch, TensorFlow, or JAX, including how models are transformed and executed.
• A background in working across teams to ship reliable, scalable tools in fast-paced engineering environments.

• How to build compiler infrastructure that supports both training and inference at scale across custom chip architectures.
• New approaches for human-in-the-loop optimization using TT-Explorer and other internal tooling.
• Best practices for evolving MLIR dialects like TTIR, TTNN, and TTKernel to support next-generation AI workloads.
• How Tenstorrent delivers open, performant, and developer-friendly AI infrastructure that scales with industry demands.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Software Engineer on the Metal Runtime team at Tenstorrent, you’ll work on the low-level software that powers our AI accelerators. You’ll build and optimize high-performance runtime systems that execute directly on the hardware, focusing on scheduling, memory movement, and efficient execution across massively parallel processors. We believe runtime systems are a core part of performance: they determine how hardware resources are utilized, how data flows through the system, and how efficiently workloads are executed at scale.

If you enjoy pushing performance, working close to the metal, and solving complex systems challenges at the hardware/software boundary, this is your kind of role.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Strong coder in C or C++, and love working close to hardware.
• Comfortable thinking in terms of threads, processors, and memory movement, and experienced writing fast, parallel code across multiple processors.
• Enjoy optimizing execution, scheduling, and memory systems for performance at scale.
• Comfortable debugging at the hardware/software boundary and reasoning about system behavior end-to-end.
• Curious about how runtimes and bare-metal software come together to power AI.
• Collaborative by nature and enjoy solving tough problems with smart people.

What We Need

• Build and optimize the Metal runtime that executes directly on our AI accelerators.
• Develop bare-metal systems that manage compute execution, scheduling, and resource utilization.
• Optimize memory movement and data flow across massively parallel hardware.
• Work closely with hardware teams to maximize performance and efficiency of our architecture.
• Debug, analyze, and tune runtime behavior across complex, distributed systems.

What You Will Learn

• How to design high-performance runtime systems for cutting-edge AI hardware.
• How execution, scheduling, and memory systems interact at scale.
• How to make custom ASICs and co-processors work efficiently across the chip.
• Best practices for debugging complex, performance-critical software.
• How software and hardware co-evolve in a fast-paced AI startup.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors.
Our diverse team of technologists have developed a high performance RISC-V-based CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a talented engineer to join our CPU design team to drive infrastructure for performance analysis, correlation and verification. You’ll work on a CPU based on RISC-V ISA, collaborating with core architects and RTL teams to deliver a highly efficient and performant design.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Great at identifying problems and developing solutions.
• Enjoys building tools and optimizing work flows.
• Skilled in C++ and Python, with an understanding of industry-standard tools for compilation, simulation and emulation.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre-silicon environments.
• Knowledgeable in architecture and microarchitecture of high-performance CPU cores.
• Ideal candidates would possess experience in infrastructure, methodology and performance verification.

What We Need

• Join a team driving improvements in CPU microarchitecture, verify performance and correlate with the RTL.
• Enhance design environment, tools, and methodologies to improve development efficiency.
• Collaborate closely with RTL engineers and core architects to meet performance goals, debug miscorrelation and verify performance features.
• Use innovative techniques to optimize power, performance, and area while driving performance experiments and evaluating results.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through performance convergence and validation.
• Hands-on experience optimizing CPU designs in both pre-silicon and post-silicon phases.
• Integration of open-source and industry-standard tools to improve flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Tenstorrent is building the world’s fastest, most efficient AI compute clusters. TT-Fabric is the high-performance nervous system of this platform: the low-level networking layer that lets thousands of RISC-V and AI processors snap together into a single, massively parallel distributed supercomputer. If you love squeezing nanoseconds out of hot paths, designing protocols that move data at absurd scale, and turning messy hardware constraints into elegant distributed systems, this is an opportunity to shape the fabric that future AI models will run on

This role is hybrid based out of Santa Clara, CA; Austin, TX; or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who We Are

• Strong systems engineer with deep C or C++ experience and comfort working in low-level or bare-metal environments.
• Passionate about hardware-software interaction, performance tuning, and eliminating inefficiencies at the protocol level.
• Curious about networking, synchronization, and communication across large clusters.
• Comfortable reasoning from first principles and challenging industry conventions.
• Motivated by building infrastructure that directly impacts large-scale AI training and inference performance.

What We Need

• Architect, implement, and maintain TT-Fabric, our low-level networking library powering distributed inference and training.
• Design scalable communication systems capable of coordinating thousands of AI processors efficiently and reliably.
• Optimize protocols, synchronization strategies, and data movement to extract maximum hardware performance.
• Integrate TT-Fabric APIs into the broader programming model in collaboration with AI and hardware teams.
• Help define the long-term architecture of Tenstorrent’s distributed systems stack.

What You Will Learn

• How large-scale AI clusters are architected from the networking layer up.
• The performance characteristics of custom AI hardware and RISC-V processors at scale.
• Advanced synchronization, collective communication, and interconnect optimization techniques.
• How distributed systems design decisions directly influence model throughput and training efficiency.
• How hardware and networking software co-evolve in next-generation AI infrastructure.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we build open, state of art compute for real workloads and real developers.

You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are 

• You bring 8+ years in CPU verification or closely related digital design.
• You know high‑performance out‑of‑order CPU microarchitecture in depth.
• You work comfortably with RTL, waveforms, logs, and complex debug scenarios.
• You communicate clearly across design, DV, emulation, and post‑silicon teams.

What We Need 

• Plan and drive functional verification for CPU core features and microarchitectural scenarios.
• Develop UVM, assembly, and C/C++ stimulus for ISA and microarchitectural coverage.
• Develop/debug C++ functional models of RISC-V extensions and un-core components such as APIC and IOMMU.
• Debug simulation and emulation regressions using waveforms, logs, and RTL understanding.
• Build and refine coverage models to track and close architectural and microarchitectural coverage.
• Improve core, cluster, and chip‑level testbenches and debug infrastructure.
• Support design bring‑up across simulation, emulation, and post‑silicon environments.
• Collaborate with design, test, and validation to deliver robust CPU cores and clusters.

What You Will Learn 

• How Tenstorrent designs and validates high‑performance RISC‑V CPU cores and clusters.
• Techniques for spanning pre‑silicon, emulation, and post‑silicon verification with shared stimulus.
• Ways to scale coverage, debug, and infrastructure across multiple CPU programs.
• How open hardware and software fit into Tenstorrent’s broader compute roadmap.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are seeking an IP Software Generalist to develop and optimize the software stack for our IP customers, enabling them to successfully integrate our AI and RISC-V hardware into their systems. In this role, you will build and support a versatile range of software components, from bare-metal firmware and drivers to system-level tools and APIs, ensuring a seamless customer experience. You will partner closely with hardware engineering, IP delivery, customer support, and product teams to deliver robust, scalable, and high-performance software solutions tailored to diverse customer architectures. Success in this role requires adaptability, strong system-level debugging skills, and the ability to bridge the gap between complex hardware IP and user-friendly software integration.

This role is hybrid, based out of Austin, TX; Toronto, ON; or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced software engineer with a strong foundation in C/C++, system programming, and low-level software design.
• Background in firmware, device drivers, embedded systems, or hardware-software co-design.
• Skilled at navigating and troubleshooting complex, full-stack software environments.
• Known for working effectively with cross-functional teams and external customers to resolve integration challenges.
• Able to balance versatile, hands-on coding with high-level architectural problem-solving.

What We Need

• Develop, optimize, and maintain software components for Tenstorrent’s hardware IP offerings.
• Define and build reference software, SDKs, and toolchains to streamline the customer integration process.
• Diagnose and resolve complex hardware/software interaction issues during customer bring-up and deployment.
• Drive the creation of high-quality documentation, test suites, and integration guides for IP software deliverables.
• Partner cross-functionally with hardware and architecture teams to ensure future IP designs are optimized for software usability.

What You Will Learn

• How to build and deploy robust software stacks for cutting-edge AI and RISC-V silicon IP.
• How to drive successful hardware-software integration across a diverse range of customer environments and architectures.
• Firsthand exposure to the complete silicon IP lifecycle, from initial bring-up to massive-scale customer deployment.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is looking for a Staff Product Development Engineer - ATE Content Developer, who will be focused on core content development for high-performance AI/ML silicon. They  will be responsible for developing production test programs on ATE test platforms, translating DFT/ATPG content into optimized ATE solutions, and implementing Streaming Scan Network (SSN) architectures for efficient test data delivery. High level challenges include reducing test cost while maintaining coverage targets, optimizing test time for chiplet and multi-die architectures, and enabling rapid yield learning through robust test methodologies. The work is done collaboratively with a group of highly experienced engineers across DFT, design, product, and manufacturing domains.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced semiconductor test engineer with 7 years and a BS/MS in EE/ECE/CE and a track record testing complex digital devices on advanced nodes.
• Hands-on with Advantest V93K and/or Teradyne UltraFlex+ platforms, comfortable owning production test programs end‑to‑end.
• Deeply familiar with DFT/ATPG flows and test architectures: scan chains, MBIST, compression, JTAG/IEEE 1149.1, and common fault models (stuck‑at, transition, path delay, cell‑aware).
• Proficient in C/C++ or Java, with strong scripting skills in Python, Perl, or TCL to automate flows, pattern handling, and data analysis.
• Skilled at debugging across ATE hardware, test programs, and silicon, and at using data to drive root‑cause analysis and yield improvement.

What We Need

• Develop and optimize production test programs on Advantest V93K using the SmarTest 8 environment, from bring‑up through high‑volume manufacturing.
• Translate ATPG patterns (STIL/WGL) into production‑ready test content, balancing test time, coverage, and cost for chiplet and multi‑die AI/ML devices.
• Implement and debug Streaming Scan Network (SSN) based content for high‑speed scan delivery, ensuring robust and scalable scan test infrastructure.
• Own test content for scan, BIST, and memory test structures, collaborating with DFT teams on pattern debug, fault diagnosis, and coverage improvement.
• Support silicon bring‑up and debug in the lab and at manufacturing sites, including correlation, corner characterization, and PVT studies.
• Build and maintain automation scripts and test methods that improve productivity, repeatability, and quality across the test lifecycle.
• Document test architectures, flows, and debug procedures so they can be scaled across products, sites, and engineering teams.

What You Will Learn

• How to test and scale cutting‑edge AI/ML silicon with chiplet and multi‑die architectures, including exposure to 2.5D/3D packaging and HBM integration.
• Deeper expertise in SSN architectures, high‑speed scan delivery, and next‑generation DFT/test methodologies for complex HPC/AI devices.
• How to drive end‑to‑end yield learning: from ATE data and STDF analytics through to design, DFT, and manufacturing process feedback.
• How a fast‑growing AI hardware startup coordinates DFT, design, product, and manufacturing to bring new silicon from first silicon to high‑volume production.
• Opportunities to influence test strategy, infrastructure, and automation roadmaps for future products and platforms as Tenstorrent’s portfolio scales.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Software Engineer on the Metal Runtime team at Tenstorrent, you’ll work on the low-level software that powers our AI accelerators. You’ll design fast, efficient runtime systems that run close to the hardware, and define the host and device APIs that expose these capabilities to the rest of the software stack. We believe APIs are a core part of systems design: they encode hardware semantics, performance tradeoffs, and concurrency models, and they live longer than any single implementation.

If you enjoy pushing performance, working close to the metal, and designing abstractions that make complex systems usable without sacrificing control, this is your kind of role.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Strong coder in C or C++, and enjoy working close to hardware.
• Comfortable thinking in terms of threads, processors, and memory movement.
• Care deeply about API design, abstraction boundaries, and developer experience in low-level systems.
• Experienced (or interested in) designing libraries or interfaces used by other engineers.
• Think about long-term maintainability, usability, and clarity when designing systems.
• Curious about how runtimes and bare-metal software come together to power AI.
• Collaborative by nature and enjoy solving tough problems with smart people.

What We Need

• Design and evolve host and device APIs that expose Metal runtime capabilities clearly and efficiently.
• Translate low-level hardware behavior into intuitive, high-performance abstractions.
• Collaborate closely with runtime, kernel, and higher-level software teams to align API design with real-world usage.
• Ensure APIs balance performance, control, safety, and ease of use.
• Contribute to runtime implementation where needed to support API design and integration.
• Debug, analyze, and improve usability and performance across the software stack.

Nice to have:

• Experience designing or evolving non-trivial C++ APIs used by other engineers.
• Familiarity with APIs for accelerator systems (e.g., CUDA, SYCL, Vulkan, or similar).

What You Will Learn

• How to design APIs and abstractions for cutting-edge AI hardware.
• How to balance performance, control, and usability in low-level system design.
• How to translate hardware capabilities into clean, developer-friendly interfaces.
• Best practices for building maintainable, high-performance systems software.
• How software and hardware co-evolve in a fast-paced AI startup.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As our TT-Distributed Software Engineer, you will develop and optimize distributed software systems that power the most efficient and highest-performing AI and HPC clusters. In this role, you'll work on distributed programming across multiple nodes, utilizing systems programming, inter-node communication, and Tenstorrent’s scalable architectures to advance the state-of-the-art distributed inference and training infrastructure.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Strong C or C++ engineer with solid foundations in systems programming, operating systems, and distributed systems principles.
• Enthusiastic about distributed computing, including IPC, socket programming, and cluster resource coordination.
• Comfortable reasoning about scalability, fault tolerance, and performance across multi-node environments.
• Curious and first-principles thinker who challenges conventional approaches to distributed system design.
• Motivated to grow into a deep technical expert in large-scale distributed AI infrastructure.

What We Need

• Architect, implement, and optimize distributed software systems that coordinate computation and communication across clusters of AI accelerators and CPUs.
• Design and build distributed APIs enabling data-parallel and tensor-parallel AI workloads.
• Leverage MPI-based technologies and related frameworks to scale programming models across multiple hosts and compute nodes.
• Develop robust systems using IPC, inter-node sockets, and distributed communication primitives to ensure reliability and high performance.
• Build and maintain testing, debugging, profiling, and monitoring tools for large-scale distributed workloads and collaborate with model and systems teams on cluster bring-up.

What You Will Learn

• How large-scale distributed inference and training systems are architected across thousands of accelerators.
• Advanced techniques in collective communication, synchronization, and parallel workload distribution.
• The performance characteristics of Tenstorrent hardware in multi-node cluster environments.
• How distributed programming models integrate with compilers, runtimes, and AI frameworks.
• The real-world challenges of deploying, debugging, and scaling next-generation AI clusters.

Our Tensix Team is building the future of AI compute with a ground-up architecture centered on scalable RISC-V processors. As we push performance boundaries, we’re reimagining the frontend of our RISC-V cores to deliver major gains in programmability, efficiency, and developer experience. This is a rare opportunity to shape the CPU architecture at the heart of our AI platform and lead one of the most strategic technical efforts at Tenstorrent.

This role is hybrid, based out of Toronto, ON or Austin, TX.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced architect with over 10 years in CPU performance modeling and microarchitecture.
• Proficient in C++ and Python, with a strong understanding of RISC-V instruction-set.
• Well versed in compiler design and how software stacks impact CPU performance and programmability.
• Familiar with open-source RISC-V cores and LLVM toolchains, including adding custom optimization passes.

What We Need

• Analyze AI workloads to identify CPU performance requirements and bottlenecks.
• Architect custom RISC-V CPU cores optimized for performance, power, and area.
• Design custom instructions that improve performance without sacrificing programmability.
• Collaborate across compilers, software, and hardware teams to co-design Tenstorrent’s next-gen compute architecture.

What You Will Learn

• How modern AI models stress CPU architecture and influence design decisions.
• The interplay between compiler design, CPU microarchitecture, and real-world performance.
• How Tenstorrent’s unified hardware-software stack enables breakthrough performance for general-purpose AI compute.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Hudson River Trading (HRT) is a quantitative trading firm at the forefront of technological innovation. We build and deploy cutting-edge systems within one of the world’s most advanced computing environments to power our global trading operations. Our non-siloed, collaborative coding environment empowers talented engineers to make significant contributions and see their impact daily. At HRT, you'll be challenged to solve the most complex problems in trading alongside many of the brightest minds in the field.

We are seeking highly motivated and skilled Research Engineers who will work very closely with our Algo Developer (Quant Research) trading teams. These roles require exceptional programming fundamentals, a strong user focus, and the ability to thrive in a fast-paced environment with constantly evolving requirements. Multitasking and context switching are inherent aspects of this role, through which you will gain insight into the ideation and execution of some of the world's most sophisticated trading strategies.  

Research Engineers at HRT work on a wide variety of projects. Examples include:

• Designing highly customized quantitative systems that enable Algo Developers to easily express and backtest new predictive signals.
• Building world-class research tooling to speed up Algo Developers’ research iteration.
• Aiding the development and deployment of very large deep learning models for HRT’s live trading.
• Improving HRT’s monetization systems which turn our predictions into profitable trades.
• Evaluating sim vs. live differences to improve the fidelity of our simulations.
• Building systems to monitor and manage live trading.
• Specializing in specific time horizons, from high frequency trading to mid-to-low frequency hedge fund-style strategies.
• Working across a very wide variety of asset classes (from equities to fixed income to options) and regions (from North America to Asia Pacific) – you’ll interact with markets across the world!

Responsibilities

• Design, develop, and maintain robust, performant, and scalable software systems.
• Optimize existing codebases for performance, reliability, and efficiency.
• Debug complex issues across distributed systems in a time-sensitive environment.
• Optimize both the mechanics and ergonomics of Algo Developer research workflows; this requires developing a deep intuition for research methodologies.
• Balance the short term goals of individual trading teams with the longer term goals of HRT’s generalized trading platforms across trading teams. Because we don’t work in a pod environment, REs on different trading teams are expected to share technology and ideas.

Qualifications

• Completed a Bachelor's or Master's degree in Computer Science, Engineering, or a related technical field. If you are currently pursuing your Bachelor's degree, please apply to our Campus/New Grad opportunities.
• Previous experience at a top-tier finance or technology company with an excellent track record of rapid advancement and superlative reviews.
• Experience with supporting internal users is preferred; bonus if you have real hands-on experience with quant research and/or ML/Deep Learning platforms.
• Experience with python numerical, ML and data-oriented libraries is a big plus (e.g. pandas, scikit, pytorch, etc.)
• Candidates should be prepared for technical interviews in either Python or C++. While there is no hard language requirement for RE roles, proficiency in one of these languages will be assessed during the interview process.
• Kindness and empathy is a real requirement. No “smart jerks” at HRT. 
• Strong understanding of data structures, algorithms, and design principles.
• Excellent communication skills, both written and verbal.
• HRT ships every day. The ability to thoughtfully, methodically, and reliably deploy new software and features is a critical skill. 
• If you have management experience, that’s always a bonus – but even so, expect to code!

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

For more info about interviewing at HRT, see this blog!

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications 

• Superb debug and analytical skills 
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

FPGAs and ASICs are critical pieces of our technology stack. We are looking for talented hardware developers to architect and design complex systems on a highly collaborative global team. In this role, you'll identify efficient ways to perform on-the-fly transformations of market data and implement models with complex data structures in RTL. Deep knowledge of SystemVerilog, FPGA internals and/or ASIC primitives, computer architecture, and vendor tool suites are essential to succeeding in this role. Expertise in networking protocols, CPU design, and/or machine learning accelerators is a big plus. No financial experience is necessary.

Responsibilities

• Collaborate with a cross-functional team to develop and deploy custom FPGA and/or ASIC solutions for a wide range of trading applications
• Investigate new technologies and tools
• Contribute to a nimble hardware development tech stack

Qualifications

• Ability to describe hardware designs at a high level, low level, or anywhere in between
• Brilliant design, optimization, debugging and problem solving skills
• Professional experience (2+ years) in RTL design for FPGA or ASIC
• Expert SystemVerilog development skills with a thorough understanding of the language 
• Expert on low level FPGA or ASIC architectures, with a deep understanding of what makes them "tick"
• Skilled in network communications, processing pipelines, and/or machine learning
• Working knowledge of Python and/or C++
• Comfortable in a Linux environment
• Strong verification experience
• Familiarity with AMD Vivado is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

Hudson River Trading (HRT) is a leading quantitative trading and investment firm specializing in multi-asset class strategies. At the core of our success lies the power of our compute cluster, the foundation where all our trading strategies are conceived and refined.

We’re looking for innovative minds to enhance the data storage libraries and tools leveraged by our Research teams to generate cutting-edge strategies. As a Storage Developer, you’ll dive deep into C++ and advanced storage solutions, working at massive scale to enable groundbreaking research. Surrounded by a team of exceptional developers constantly pushing the boundaries of their expertise, you’ll be amazed at the impact you can achieve.

Profile

• You’re able to talk both high-level distributed systems design trade-offs and low-level OS-level details
• You’re able to balance being detail-oriented with good prioritization of what matters now vs. later
• You thrive in collaborative environments and have a strong sense of ownership
• In your spare time you code, tinker, read, explore, break things, and have an insatiable curiosity for all things computer related

Responsibilities

• Work with a small team of skilled developers to create distributed storage systems customized to fit HRT’s needs
• Stay informed about the current “state of the art” and help bridge the gap between here and there
• Understand our Research team’s storage and compute needs, and build for the next generation of research

Qualifications 

• Proficient C++ experience is required, daily use preferred 
• Distributed systems experience required (ability to reason about fault tolerance, sharding, trade-offs, and designing for simplicity and robustness under failure) 
• Previous experience developing databases, distributed filesystems, search infrastructure, or similar ideal but not required 
• Ability to work productively in a Linux environment
• Knowledge of UNIX operating systems, low-level systems-level performance issues, and networking

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.