𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟮𝟬𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟴𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟮𝟬-𝟴𝟬 𝗟𝗣𝗔)

Experience: 4+ yrs

Location: Bengaluru

Job Type: Full-time

We are seeking a highly skilled Senior Static Timing Analysis (STA) Engineer to lead timing analysis, optimization, and signoff activities for complex ASIC and SoC designs. This role is ideal for professionals with deep expertise in static timing analysis, timing closure, and signoff methodologies who are passionate about delivering high-performance semiconductor solutions on advanced technology nodes.

As a Senior STA Engineer, you will collaborate closely with RTL, Physical Design, DFT, and Verification teams to ensure timing convergence across multiple operating conditions. You will play a critical role in driving timing closure, validating design constraints, supporting engineering change orders (ECOs), and developing efficient automation workflows that improve design quality and productivity.

Requirements

Key Responsibilities

• Perform full-chip Static Timing Analysis (STA) and timing signoff for complex ASIC and SoC designs.
• Analyze and resolve setup, hold, recovery, and removal timing violations to achieve timing closure.
• Execute Multi-Mode Multi-Corner (MCMM) timing analysis across multiple process, voltage, and temperature (PVT) conditions.
• Develop, validate, and maintain SDC timing constraints and timing exception methodologies.
• Collaborate with RTL, Physical Design, DFT, and Verification teams to optimize timing, power, and area (PPA).
• Analyze timing reports, identify critical paths, and implement optimization strategies to improve design performance.
• Support ECO implementation and timing validation throughout the design lifecycle.
• Develop automation scripts using TCL, Python, or Perl to streamline STA analysis and reporting workflows.
• Participate in design reviews, timing signoff activities, and technical discussions to ensure high-quality design delivery.
• Contribute to continuous improvement of STA methodologies, automation frameworks, and signoff processes.

What Makes You a Great Fit

• 5+ years of hands-on experience in ASIC Static Timing Analysis (STA) and timing signoff.
• Strong expertise in Synopsys PrimeTime for timing analysis and signoff.
• Solid understanding of MCMM timing analysis, timing closure, and signoff methodologies.
• Experience working with SDC constraints, timing exceptions, ECO flows, and clock architecture.
• Strong knowledge of setup/hold analysis, timing optimization, and performance improvement techniques.
• Proficiency in TCL scripting, with Python or Perl scripting experience considered an advantage.
• Familiarity with Cadence Tempus, Cadence Innovus, and Physical Design workflows is preferred.
• Experience working on advanced semiconductor technology nodes such as 16nm, 7nm, 5nm, or below is highly desirable.
• Strong analytical, debugging, communication, and cross-functional collaboration skills.
• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related discipline, with the ability to deliver high-quality solutions in a fast-paced engineering environment.