The Role 

The Senior Systems Software Engineer will be a member of the core team building the Quantum Key Distribution system. The focus is on high-performance Python services on Linux, algorithm optimization and acceleration (also via hardware offload), and the role spans defining software architecture, integrating with FPGA/embedded subsystems, and turning requirements into reliable, observable software.  

The Senior Systems Software Engineer leads and co-owns the overall internal QKD software architecture and client-facing software API. By setting engineering standards, mentoring, and unblocking delivery, they ensure predictable releases and a strong execution cadence. 

The Responsibilities 

The Senior Systems Software Engineer should expect to work in the following activities. 

• System architecture
  • Leading and co-owning the QKD software architecture: control plane services, key sifting/postprocessing integration, configuration management, monitoring, and external interfaces 
  • Defining module boundaries and service APIs; evolving the system toward clear data/control-plane separation 

• Efficient implementation and hardware/software integration
  • Designing and implementing high-performance Python services on Linux (asyncio, WebSockets, NumPy); profiling and tuning for latency and throughput
  • Developing, profiling, and optimizing QKD sifting and postprocessing algorithms (signal handling/processing, error correction/information reconciliation, LDPC, privacy amplification) to maximize key rate and minimize end-to-end latency; applying algorithmic improvements and implementation techniques (vectorization, concurrency/async, memory/layout tuning, C/C++ extensions, SIMD/CUDA/GPU/FPGA offload where appropriate)
  • Defining and maintaining robust interfaces with embedded/FPGA system components over UART/USB/PCIe/Ethernet; respecting realtime constraints and failure modes 
  • Guiding downstream system integration (WebSockets/gRPC/REST) and ensuring clear contracts and backward compatibility
  • Designing for test – building mocks/simulators and automated test systems 

• DevOps
  • Building and maintaining CI/CD with Docker and GitHub Actions; automated tests, static analysis, artifact management, and release pipelines
  • Establishing observability (structured logging, metrics, tracing) and operational runbooks; improving reliability and debuggability with SLOs/alerts
  • Embedding security and crypto hygiene by default: secure transport, secrets management, key handling, and coordination with cryptography stakeholders
  • Adding performance benchmarking and regression tracking for key rate and end-to-end latency; integrating profiling/flame graphs into CI and enforcing performance budgets 

The Requirements 

The Senior Systems Software Engineer is expected to have the following qualifications and experience. 

• 5+ years of Python development; 3+ years leading or co‑owning service/system architecture for a hardware‑first product 

• Strong Linux async Python (asyncio, WebSockets), concurrency (threads/processes), profiling/tuning 

• Proven custom hardware integration (MCU, FPGA) over UART/USB/PCIe/Ethernet 

• CI/CD with Docker and GitHub Actions; automated testing, static analysis, artifact management 

• Experience with GPU & CUDA acceleration/optimization; SIMD familiarity 

• Production observability (logging/metrics/tracing) and incident/debug practices 

• Working knowledge of relational/key-value/time-series stores (PostgreSQL/Redis/Prometheus)  

• Security by Default mindset: secrets, secure transport, key/crypto hygiene 

• Proficiency in written and spoken English 

• Ability to be on-site in Munich office several times per week 

• Applicants must have the right to work in Germany at the time of application. We do not provide visa sponsorship. 
• Must be eligible to obtain and maintain either (a) a U.S. Secret (or higher) security clearance or (b) an EU SECRET (or national equivalent) personnel security clearance. Employment is contingent on meeting applicable government security requirements; eligibility is determined by the competent authorities.

Good to have: 

• Experience with QKD systems, cryptography, or high‑rate data pipelines  

• Exposure to C/C++ for low‑level interfacing and FPGA/embedded ecosystems  

• Familiarity with gRPC/Protobuf, schema/versioning strategies, and Kubernetes 

The Role 

The Senior FPGA Developer will be a member of the core team building the Quantum Key Distribution system. The focus is end‑to‑end RTL ownership on AMD/Xilinx (Artix‑7, Kintex UltraScale): architect, implement, verify, and close timing on high‑rate interfaces and deterministic pipelines. The role also sets engineering discipline for FPGA development and mentors a junior engineer. 

The Senior FPGA Developer owns the FPGA architecture/codebase and collaborates closely with embedded/software to define clean contracts, ensure reliable bring‑up, and deliver reproducible, versioned bitstreams. 

The Responsibilities 

The Senior FPGA Developer should expect to work in the following activities. 

• RTL architecture, interfaces, and rather high-speed datapaths
  • Owning SystemVerilog RTL architecture/implementation for Artix‑7 and Kintex UltraScale (SystemVerilog, Vivado)
  • Implementing DDR3/DDR4 controllers integration, PCIe endpoint/DMA, and Ethernet/SFP paths; evaluating/integrating third‑party MAC/PCS IP
  • Building deterministic acquisition/timing/sifting layers — packetization, buffering, alignment; robust clocking/CDC/reset; custom low‑level protocols —  and bridging them to high‑throughput interfaces (DDR/PCIe)
  • Defining clear AXI/AXI‑Stream boundaries and register maps for SW/FW integration 

• Constraints, timing closure, and floorplanning
  • Authoring and maintaining XDC constraints (clocks, I/O, exceptions); achieving consistent timing closure across corners
  • Applying practical floorplanning (pblocks, placement guidance) and CDC methodology; analyzing reports and iterating for margin 

• Verification and CI
  • Establishing a professional verification environment with ModelSim/Questa; developing self‑checking testbenches and regression suites; integrating Python/cocotb co‑simulation with software harnesses/mocks; defining coverage goals (OSVVM/UVM as appropriate)
  • Building CI for lint/sim/synth/impl; archiving reports/bitstreams; automating regressions (including cocotb) and basic HW‑in‑the‑loop smoke tests 

• Bring-up, debug, and releases
  • Board bring-up and debug using ILA/logic analyzers; link training, memory calib, and protocol bring-up
  • Owning bitstream packaging, versioning, and release notes; ensuring reproducible builds and traceable artifacts 

• Cross-team collaboration and mentoring
  • Driving system integration with SW/FW: register/driver contracts, throughput/latency budgets, HIL
  • Mentoring a junior engineer; codifying style guides, reviews, and design documentation 

The Requirements 

The Senior FPGA Developer is expected to have the following qualifications and experience. 

• 5+ years production FPGA on AMD/Xilinx; expert SystemVerilog RTL 

• Demonstrated mentoring of junior engineers 

• Strong constraints/timing (XDC), CDC/reset, and practical floorplanning; consistent timing closure 

• Hands‑on DDR3/DDR4, PCIe endpoints/DMA, Ethernet/SFP; integrating/evaluating third‑party MAC/PCS IP 

• Strong verification background; experience with self-checking testbenches and regression testing, proficiency with ModelSim/Questa. Knowledge of OSVVM/UVM is a plus 

• CI for HDL: scripted sim/synth/impl (Tcl/Make/Python), lint, artifact/version management; board bring‑up and ILA‑based debug 

• System integration with SW/FW: register maps, driver contracts, HIL 

• Proficiency in written and spoken English 

• Ability to be on-site in Munich or Potsdam offices to work with hardware, when required
• Applicants must have the right to work in Germany at the time of application. We do not provide visa sponsorship.
• Must be eligible to obtain and maintain either (a) a U.S. Secret (or higher) security clearance or (b) an EU SECRET (or national equivalent) personnel security clearance. Employment is contingent on meeting applicable government security requirements; eligibility is determined by the competent authorities.

Good to have: 

• AXI4/AXI‑Stream expertise and DMA performance tuning 

• Formal verification exposure 

• Scripting for automation (Python/Tcl) and CI systems (GitHub Actions/Jenkins) 

• MicroBlaze/Zynq ecosystems and low‑level FW/C driver collaboration 

• Proven delivery on Artix‑7 and/or Kintex UltraScale with Vivado 
   

The Role 

The Electronics Design Engineer will be a member of the hardware team delivering low‑noise, high‑frequency mixed‑signal control and instrumentation for our QKD systems. The role spans end‑to‑end board design in Altium (schematics, layout, DFM/DFT), precision analog signal chains, prototype bring‑up/validation, and, where needed, STM32 (F4/H7) firmware in C for control, calibration, and integration. You will work with existing automated measurement software in Python and extend it where needed, collaborate closely with optics, FPGA, and software, and support manufacturing. 

The Responsibilities 

The Electronics Design Engineer should expect to work in the following activities. 

• Hardware design, prototyping, and validation 
  • Owning hardware architecture and component selection for precision, lownoise, and highfrequency performance 
  • Designing lownoise analog and mixedsignal schematics and PCB layout in Altium 
  • Managing prototype builds and vendors; executing bringup; precision and highfrequency measurements (DC accuracy, noise spectral density, longterm drift, frequency response); lab debug and reworks 
  • Working with existing automated measurement software (Python) and extending it where needed 
• Firmware development on STM32 and interfacing in Python (secondary scope)
  • Designing and modifying STM32 F4/H7 firmware in C (HAL)
  • Interfacing with Python drivers/scripts for control and data acquisition 

• Test automation and CI
  • Building and extending automated board/firmware test setups (Python; instrument control via VISA/SCPI through the existing automated measurement software) to capture logs/metrics
  • Establishing repeatable build/test pipelines for firmware and board validation; archiving artifacts, measurements, and calibration data 

• Manufacturing support and releases
  • Producing manufacturing packages; supporting vendors through fabrication and assembly; designing/maintaining simple test fixtures
  • Owning hardware/firmware versioning and release notes; maintaining traceable revisions 

• Cross‑team collaboration and documentation
  • Collaborating with optics/FPGA/software on interfaces, calibration, timing/latency budgets, and integration
  • Authoring design docs, analyses and budgets, calibration/bringup procedures, and change logs
  • Maintaining detailed experimental documentation in Confluence 

The Requirements 

The Electronics Design Engineer is expected to have the following qualifications and experience. 

• 5+ years analog/mixedsignal electronics design for R&D/instrumentation; strong Altium for schematics and PCB layout; DFM/DFT 

• Deep analog fundamentals: lownoise signal chains (e.g., highfrequency TIAs/preamps, ADC drivers, antialiasing/reconstruction filters), precision references/measurements, grounding/guarding/shielding, lowleakage layout 

• Ability to set/close noise and error budgets; tolerance/Monte Carlo and worstcase analysis; SPICEclass simulation (LTspice/PSPICE, etc.) 

• Lab expertise: precision/HF measurements (DC accuracy, noise spectral density, longterm drift, frequency response, temperature dependency); oscilloscopes, spectrum analyzers; VNA as applicable 

• Awareness of EMC/EMI and safety constraints; designforcompliance and precompliance testing 

• Python for lab/test automation and instrument control; Git‑centric workflow 

• Proficiency in written and spoken English 

• Ability to be on‑site in Munich or Potsdam offices to work with hardware, when required 

• Applicants must have the right to work in Germany at the time of application. We do not provide visa sponsorship. 
• Must be eligible to obtain and maintain either (a) a U.S. Secret (or higher) security clearance or (b) an EU SECRET (or national equivalent) personnel security clearance. Employment is contingent on meeting applicable government security requirements; eligibility is determined by the competent authorities.

Good to have: 

• STM32 F4/H7 exposure; C with HAL 

• Familiarity with STM32 bootloaders/updates (DFU/OTA) 

• Experience with calibration flows and production test fixtures

The Role

The Lead Researcher in Quantum Machine Learning will be a member of Terra Quantum's AI Applied Research team. This team is at the forefront of conducting both fundamental and applied research in the field of quantum machine learning. Although the Lead Researcher will focus on innovating in quantum machine learning, the role involves translating research findings into practical algorithmic software solutions. The Lead Researcher is expected to closely monitor and analyse scientific and industrial trends and needs across short-term, mid-term, and long-term horizons, specifically within the quantum technology and machine learning sectors, to guide the development and implementation of hybrid quantum-classical algorithms.

Reporting directly to the Director of AI, the Lead Researcher in Quantum Machine Learning plays a pivotal role in driving excellence within their team. They are not only detail-oriented but also possess a remarkable capacity for enthusiasm. By demonstrating commitment and passion for the mission, they inspire their team members to contribute to making quantum technologies widely accessible and to effect positive change globally.

The Responsibilities

The Lead Applied Researcher should expect to work in the following Quantum Machine Learning Team activities.

• Fundamental research in quantum machine learning
  • Developing quantum machine learning algorithms for different data processing tasks, e.g. time series, routing and planning, image, graph data, or natural language processing
  • Keeping up with state-of-the-art approaches in quantum machine learning
  • Analysing parametrised quantum circuits in their capacity to learn via a hybrid quantum-classical optimization loop
  • Utilizing metrics of, e.g., the Fisher information matrix, the effective dimension, and Fourier terms accessibility for parametrized quantum circuit ansatz analysis
  • Improving the trainability of parametrised quantum circuits through layerwise batch-entropy regularization and similar techniques
  • Interpreting and explaining quantum machine learning models. Analysing the flow of information through different architectures of quantum neural networks
  • Researching and understanding where the quantum brings the benefit to machine learning
  • Developing data encoding and data processing techniques for different types of quantum computers
  • Assisting in writing patent draft applications
  • Writing research papers for scientific journals

• Efficient implementation of quantum machine learning algorithms
  • Executing quantum machine learning algorithms on QPUs, e.g. of QuEra, IonQ, Rigetti, and IBM Q
  • Adjusting and improving implementation of hybrid quantum neural networks for different QPUs
  • Exploring and testing the best ways to hybridize classical machine learning solutions with quantum machine learning
  • Understanding the way to implement an efficient interaction of hardware (CPU, GPU) and software (PyTorch, Pennylane)
  • Assisting in the development of our quantum machine learning SDK
  • Optimising, at least theoretically, the code of hybrid quantum-classical machine learning solutions for faster execution

• Supporting industry projects implementation
  • Bringing in novel ideas based on industry needs in time-series, routing and planning, GenAI, and natural language processing tasks
  • Brainstorming on possibilities of quantum machine learning algorithms applications to our client’s industry problems
  • Working on finding a theoretical or empirical advantage of using hybrid quantum-classical machine learning in industrial problems
  • Assisting in writing applied industry research papers for scientific journals

The Requirements

The Lead Applied Researcher is expected to have several qualifications depending on the area of activity in quantum machine learning.

• PhD in computer science, physics, mathematics, electrical engineering, or equivalent subject is required
• Publication record in quantum machine learning, or variational quantum algorithms is required
• Advanced expertise in one or more quantum programming languages (Qiskit, Q#, Pennylane, Cirq, Quipper, Scaffold, tket) is required
• Advanced experience working with variational quantum algorithms for machine learning is required
• Experience working with the classical machine learning algorithms is required
• Computational learning theory expertise is optional
• Expert knowledge in Python is optional
• Expert knowledge in Pytorch and TensorFlow is optional
• Experience in programming for GPUs is optional
• Experience in working with QPUs is optional
• Goal-oriented, analytical and the ability to work independently
• Flexible, proactive, and creative with the ability to work in the team
• Highly motivated and resilient with the ability to work interdisciplinary
• Proficiency in written and spoken English
• Applicants must have the legal right to live and work in the European Union or Switzerland. Unfortunately, we are unable to offer visa sponsorship for this role.

The Role

The Researcher in Quantum Machine Learning or Quantum Information will be a member of Terra Quantum's AI Applied Research team. This team is at the forefront of conducting both fundamental and applied research in the field of quantum machine learning. Although the Researcher will focus on innovating in quantum machine learning, the role involves translating research findings into practical algorithmic software solutions. The Researcher is expected to closely monitor and analyse scientific and industrial trends and needs across short-term, mid-term, and long-term horizons, specifically within the quantum technology and machine learning sectors, to guide the development and implementation of hybrid quantum-classical algorithms.

The Researcher in Quantum Machine Learning plays a role in driving excellence within their team. They are not only detail-oriented but also possess a remarkable capacity for enthusiasm. By demonstrating commitment and passion for the mission, they inspire their team members to contribute to making quantum technologies widely accessible and to effect positive change globally.

The Responsibilities

The Applied Researcher should expect to work in one and supporting in the other areas of the following Quantum Machine Learning Team activities.

• Fundamental research in quantum machine learning
  • Developing quantum machine learning algorithms for different data processing tasks, e.g. time series, routing and planning, image, graph data, or natural language processing
  • Exploring state-of-the-art approaches in quantum machine learning
  • Analysing parametrised quantum circuits in their capacity to learn via a hybrid quantum-classical optimization loop
  • Utilizing metrics of, e.g., the Fisher information matrix, the effective dimension, and Fourier terms accessibility for parametrized quantum circuit ansatz analysis
  • Improving the trainability of parametrised quantum circuits through layerwise batch-entropy regularization and similar techniques
  • Interpreting and explaining quantum machine learning models. Analysing the flow of information through different architectures of quantum neural networks
  • Researching and understanding where the quantum brings the benefit to machine learning
  • Developing data encoding and data processing techniques for different types of quantum computers
  • Writing research papers for scientific journals

• Efficient implementation of quantum machine learning algorithms
  • Executing quantum machine learning algorithms on QPUs, e.g. of QuEra, IonQ, Rigetti, and IBM Q
  • Adjusting and improving implementation of hybrid quantum neural networks for different QPUs
  • Exploring and testing the best ways to hybridize classical machine learning solutions with quantum machine learning
  • Understanding the way to implement an efficient interaction of hardware (CPU, GPU) and software (PyTorch, Pennylane)
  • Assisting in the development of our quantum machine learning SDK
  • Optimising, at least theoretically, the code of hybrid quantum-classical machine learning solutions for faster execution

• Supporting industry projects implementation
  • Bringing in novel ideas based on industry needs in time-series, routing and planning, GenAI, and natural language processing tasks
  • Brainstorming on possibilities of quantum machine learning algorithms applications to our client’s industry problems
  • Working on finding a theoretical or empirical advantage of using hybrid quantum-classical machine learning in industrial problems
  • Assisting in writing applied industry research papers for scientific journals

The Requirements

The Applied Researcher is expected to have several qualifications depending on the area of activity in quantum machine learning or quantum information.

• Currently pursuing or recently completed a degree in computer science, physics, mathematics,
  or equivalent subject
• Experience in one or more quantum programming languages (Qiskit, Pennylane, Cirq, etc.)
• Experience working with variational quantum algorithms for machine learning
• Experience working with classical machine learning algorithms
• Basic knowledge in Python, Pytorch and TensorFlow
• Experience in working with QPUs is optional
• Familiarity with quantum information theory is optional
• Familiarity with Tensor-Network techniques is optional
• Goal-oriented, analytical and the ability to work independently
• Flexible, proactive, and creative with the ability to work in the team
• Highly motivated and resilient with the ability to work interdisciplinary
• Proficiency in written and spoken English
• Applicants must have the legal right to live and work in the European Union or Switzerland. Unfortunately, we are unable to offer visa sponsorship for this role.