Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will support the implementation of complex IC physical designs, from synthesis to sign-off. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock tree synthesis (CTS), routing, and sign-off.
• Work on synthesis, timing analysis (STA), and optimisation to achieve strong PPA metrics.
• Assist in power planning and analysis, addressing IR drop, electromigration, and related effects.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Work closely with RTL and architecture teams to support design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 0–5 years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below), including internships.
• Familiarity with EDA tools for place & route, STA, and sign-off.
• Basic understanding of CMOS technology, semiconductor physics, and process limitations.
• Exposure to timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation is a plus.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Interest in working with advanced AI tools and models as part of the design workflow.
• Experience or coursework in high-performance computing (HPC), AI accelerators, or networking chips is a plus.

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

We are looking for a highly motivated and experienced RTL Design Engineer to join our dynamic team. In this role, you will play a key part in the design and implementation of digital systems, contributing to every stage of the project lifecycle. Your work will involve developing and optimising Register Transfer Level (RTL) designs for high-performance and power-efficient systems

RTL Development and Implementation:

• Develop and maintain RTL specifications for digital designs, ensuring clarity and accuracy.
• Implement complex design modules with a focus on performance, power, and area efficiency.
• Take ownership of design tasks, including planning, execution, and delivery of work packages.
• Define design tasks for the project, including partitioning, interface specifications, and module definitions.
• Collaborate with verification engineers to ensure functional correctness through simulation and formal verification.

Cross-Functional Collaboration:

• Work closely with physical design engineers, and verification teams to ensure seamless integration of the design.

Documentation and Standards Compliance:

• Document RTL design methodologies, module interfaces, and functional requirements.
• Ensure adherence to coding standards, best practices, and maintainability guidelines.

Qualifications and Skills:

Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.

Experience:

• 6+ years of experience in digital design, RTL development, or related roles.
• Proven expertise in developing RTL designs for high-performance systems.
• Familiarity with advanced digital design concepts, such as pipelining, clock-domain crossing, and power gating.
• Experience with high-speed or low-power design methodologies.

Soft Skills:

• Strong analytical and problem-solving skills.
• Effective communication and collaboration abilities in cross-functional teams.
• A detail-oriented approach with a focus on quality and efficiency.

How we work

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is

About us

• Founded in 2022, team of 70+ which is expanding rapidly
• Modern, open offices in London and Bristol
• Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency

Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will support the implementation of complex IC physical designs, from synthesis to sign-off. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock tree synthesis (CTS), routing, and sign-off.
• Work on synthesis, timing analysis (STA), and optimisation to achieve strong PPA metrics.
• Assist in power planning and analysis, addressing IR drop, electromigration, and related effects.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Work closely with RTL and architecture teams to support design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 0–5 years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below), including internships.
• Familiarity with EDA tools for place & route, STA, and sign-off.
• Basic understanding of CMOS technology, semiconductor physics, and process limitations.
• Exposure to timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation is a plus.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Interest in working with advanced AI tools and models as part of the design workflow.
• Experience or coursework in high-performance computing (HPC), AI accelerators, or networking chips is a plus.

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

We are looking for a highly motivated and experienced RTL Design Engineer to join our dynamic team. In this role, you will play a key part in the design and implementation of digital systems, contributing to every stage of the project lifecycle. Your work will involve developing and optimising Register Transfer Level (RTL) designs for high-performance and power-efficient systems

RTL Development and Implementation:

• Develop and maintain RTL specifications for digital designs, ensuring clarity and accuracy.
• Implement complex design modules with a focus on performance, power, and area efficiency.
• Take ownership of design tasks, including planning, execution, and delivery of work packages.
• Define design tasks for the project, including partitioning, interface specifications, and module definitions.
• Collaborate with verification engineers to ensure functional correctness through simulation and formal verification.

Cross-Functional Collaboration:

• Work closely with physical design engineers, and verification teams to ensure seamless integration of the design.

Documentation and Standards Compliance:

• Document RTL design methodologies, module interfaces, and functional requirements.
• Ensure adherence to coding standards, best practices, and maintainability guidelines.

Qualifications and Skills:

Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.

Experience:

• 6+ years of experience in digital design, RTL development, or related roles.
• Proven expertise in developing RTL designs for high-performance systems.
• Familiarity with advanced digital design concepts, such as pipelining, clock-domain crossing, and power gating.
• Experience with high-speed or low-power design methodologies.

Soft Skills:

• Strong analytical and problem-solving skills.
• Effective communication and collaboration abilities in cross-functional teams.
• A detail-oriented approach with a focus on quality and efficiency.

How we work

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is

About us

• Founded in 2022, team of 70+ which is expanding rapidly
• Modern, open offices in London and Bristol
• Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency

Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

We are looking for a highly motivated and experienced RTL Design Engineer to join our dynamic team. In this role, you will play a key part in the design and implementation of digital systems, contributing to every stage of the project lifecycle. Your work will involve developing and optimising Register Transfer Level (RTL) designs for high-performance and power-efficient systems

RTL Development and Implementation:

• Develop and maintain RTL specifications for digital designs, ensuring clarity and accuracy.
• Implement complex design modules with a focus on performance, power, and area efficiency.
• Take ownership of design tasks, including planning, execution, and delivery of work packages.
• Define design tasks for the project, including partitioning, interface specifications, and module definitions.
• Collaborate with verification engineers to ensure functional correctness through simulation and formal verification.

Cross-Functional Collaboration:

• Work closely with physical design engineers, and verification teams to ensure seamless integration of the design.

Documentation and Standards Compliance:

• Document RTL design methodologies, module interfaces, and functional requirements.
• Ensure adherence to coding standards, best practices, and maintainability guidelines.

Qualifications and Skills:

Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.

Experience:

• 6+ years of experience in digital design, RTL development, or related roles.
• Proven expertise in developing RTL designs for high-performance systems.
• Familiarity with advanced digital design concepts, such as pipelining, clock-domain crossing, and power gating.
• Experience with high-speed or low-power design methodologies.

Soft Skills:

• Strong analytical and problem-solving skills.
• Effective communication and collaboration abilities in cross-functional teams.
• A detail-oriented approach with a focus on quality and efficiency.

How we work

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is

About us

• Founded in 2022, team of 70+ which is expanding rapidly
• Modern, open offices in London and Bristol
• Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency

Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

Our ideal candidate could have 0-3 years’ experience, including recent graduates. This is a unique opportunity to accelerate your development, working with an experienced and collaborative team and gaining exposure to a broad range of disciplines. At Fractile, we value ideas from everyone, regardless of title or tenure, and we believe the best engineering happens when people share, question, and learn together. You’ll be joining a culture where your curiosity is encouraged, your input matters, and there’s real room to grow.

We are looking for a highly motivated RTL Design Engineer to join our dynamic team. In this role, you will play a key part in the design and implementation of digital systems, contributing to every stage of the project lifecycle. Your work will involve developing and optimising Register Transfer Level (RTL) designs for high-performance and power-efficient systems

RTL Development and Implementation:

• Develop and maintain RTL specifications for digital designs, ensuring clarity and accuracy.
• Implement complex design modules with a focus on performance, power, and area efficiency.

Cross-Functional Collaboration:

• Work closely with physical design engineers, and verification teams to ensure seamless integration of the design.

Documentation and Standards Compliance:

• Document RTL design methodologies, module interfaces, and functional requirements.
• Ensure adherence to coding standards, best practices, and maintainability guidelines.

Qualifications and Skills:

Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.

Experience:

• Experience in digital design, RTL development, or related projects.
• Familiarity with advanced digital design concepts, such as pipelining, clock-domain crossing, and power gating.
• Knowledge of high-speed or low-power design methodologies.

Soft Skills:

• Strong analytical and problem-solving skills.
• Effective communication and collaboration abilities in cross-functional teams.
• A detail-oriented approach with a focus on quality and efficiency.

About us

• Founded in 2022, team of 70+, which is expanding rapidly
• Modern, open offices in London and Bristol
• Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency

Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off, including opportunities for full-chip ownership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off, including opportunities for full-chip ownership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off, including opportunities for full-chip ownership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.