About the Role
We are seeking a versatile and experienced engineer to join our SOTA Training Platform team. This team is responsible to rapidly bring up state-of-the-art open-source models (like LLaMA, Qwen, etc) or customer-provided proprietary models on our Cerebras CSX systems. Success in this role requires a system-minded generalist who thrives in fast-paced bringup environments and is comfortable working across the entire Cerebras software stack.
Your work will play a critical role in achieving unprecedented levels of performance, efficiency, and scalability for AI applications.

• Contribute to the end-to-end bring up of ML models on Cerebras CSX systems.
• Work across the stack: model architecture translation, graph lowering, compiler optimizations, runtime integration, and performance tuning.
• Debug performance and correctness issues spanning model code, compiler IRs, runtime behavior, and hardware utilization.
• Propose and prototype improvements across tools, APIs, or automation flows to accelerate future bring ups.
• Study emerging training and post-training algorithms and map to Cerebras software architecture and hardware.

• Bachelor’s, Master’s, or PhD in Computer Science, Engineering, or a related field.
• 5+ years of relevant industry experience (internship/co-op experience included)
• Comfort navigating the full AI toolchain: Python modeling code, compiler IRs, performance profiling, etc.
• Strong debugging skills across performance, numerical accuracy, and runtime integration.
• Experience with deep learning frameworks (e.g., PyTorch, TensorFlow) and familiarity with model internals (e.g., attention, MoE, diffusion).
• Proficiency in C/C++ programming and experience with low-level optimization.
• Proven experience in compiler development, particularly with LLVM and/or MLIR.
• Strong background in optimization techniques, particularly those involving NP-hard problems.
• Familiarity with large scale ML systems and state of the art algorithms, including model training and reinforcement learning.

• Competitive salary and benefits package.
• Opportunities for professional growth and career advancement.
• A dynamic and innovative work environment.
• The chance to work on cutting-edge technologies and make a significant impact on the future of AI.

As an Infrastructure Hardware Technical Program Manager (Server and Network Systems) on the Cluster Architecture Team, you will drive end-to-end delivery of server and network platform programs across Cerebras CS-3–based AI clusters — from requirements and vendor selection through lab bring-up, qualification, and production rollout. You will be the execution owner for multi-team programs spanning OEM/ODM partners, component vendors, internal software/runtime teams and architects, validation/QA, and deployment/operations.

This role is intentionally technical: you must understand server, network, and system-level trade-offs well enough to run effective technical reviews, keep programs grounded in real constraints, and maintain a crisp decision trail - while partnering closely with the Compute / Server / Network Platform Architects for detailed technical direction and sign-off. You will also build shared understanding with our rack/elevations and physical datacenter design partners so that server and network changes land smoothly in real deployments (without owning physical DC design).

Responsibilities

• Own end-to-end program execution for server systems and network equipment in Cerebras clusters, including new platforms, refreshes, and major component/config changes.
• Drive requirements gathering and convert inputs into executable plans with clear milestones, readiness gates, and cross-functional deliverables.
• Represent Cluster Architecture in executive reviews, OKR cycles, and leadership/customer forums as needed.
• Build and manage integrated schedules across vendors and internal teams, track dependencies, critical path, and risks.
• Manage OEM/ODM and switch/vendor engagements (RFI/RFP, samples, escalations, roadmap alignment).
• Partner with Compute / Server Platform / Network Architects to turn architectural decisions into qualification plans, acceptance criteria, and rollout strategies.
• Lead qualification and release readiness (lab/staging validation, regression tracking, go/no-go decisions).
• Own risk and change management into production, including versioning, rollout sequencing, and stakeholder communication.
• Ensure operational readiness with deployment and fleet teams and maintain alignment with rack/physical DC owners on power, cooling, space, and cabling constraints.

Skills and Qualifications

• B.S. or M.S. in Computer Science, Electrical/Computer Engineering, or equivalent experience.
• 8+ years in Technical Program Management (or similar delivery leadership) for server, network, or infrastructure platforms from concept through production.
• Experience coordinating complex server and/or datacenter network programs across OEM/ODMs, switch vendors, and internal engineering teams.
• Working knowledge of server architecture (CPU/NUMA, memory bandwidth, PCIe, NIC and storage IO) and enough networking fundamentals (leaf-spine fabrics, switch platforms, high-performance interconnects) to run effective technical reviews.
• Familiarity with Linux server fleet management (provisioning, firmware/BIOS, drivers, field triage).
• Strong multi-team program execution skills: integrated plans, risk management, dependency tracking, and executive-level communication.
• Ability to operate in ambiguity and keep parallel server and network workstreams aligned.
• Experience with AI/ML, HPC, or performance-sensitive distributed infrastructure is a plus.

About The Role

As a Compute / Server Platform Architect on the Cluster Architecture Team, you will own the server-side platform architecture that enables Cerebras CS3-based AI clusters (training and inference) to deliver predictable performance, scalability, and reliability. Our accelerators are network-attached, so the x86 server fleet is a first-class part of the end-to-end system: it runs critical-path runtime functions (for example orchestration, prompt caching, and IO/control services) and must be co-designed with software for token-level latency, throughput, and cost efficiency. You will translate workload behavior into CPU, memory, IO, PCIe, and host-networking requirements, drive platform evaluations with vendors, and provide technical leadership through qualification and production adoption in close partnership with other function leaders and TPMs.

Responsibilities

• Own the architecture for all server roles in Cerebras clusters, including definitions of server types, configurations, and lifecycle strategy.
• Define and maintain server formulas (counts and ratios per CS-3 count, cluster size, and workload type) including capacity planning and headroom policy.
• Specify platform configurations: CPU SKU and core strategy, our vendor roadmap (e.g., AMD, Intel, ARM), memory topology (channels, DIMM type, capacity), PCIe topology and lane budgeting, NIC selection/placement, and local NVMe policy where applicable.
• Translate software and runtime flows into measurable hardware requirements (CPU utilization, memory bandwidth/latency, bursty IO patterns, queueing and concurrency limits) and communicate clear guardrails back to software teams.
• Develop performance and scaling models; validate with microbenchmarks and workload-level experiments; identify bottlenecks and drive cross-stack fixes.
• Define the OS, BIOS, firmware, and driver baseline for each server type; there are other teams that follow these recommendations and apply them on our fleet.
• Stay current on emerging server technologies (CPU generations, new memory technologies, CXL, NVMe evolutions, SmartNIC/DPU capabilities where relevant) and run proof-of-concept evaluations to determine when to adopt.
• Lead technical vendor engagements (OEM/ODM and component vendors): influence roadmap, request platform knobs, and drive joint debugging on performance or reliability issues.
• Define qualification and acceptance criteria (performance, stability, operability) and partner with the Infrastructure Hardware TPM to execute qualification plans and land changes cleanly into production.
• Support bring-up and rare deployment debugging in lab and staging environments; drive root-cause analysis for regressions spanning firmware, drivers, OS, and runtime behavior.

Skills and Qualifications

• PhD. in Computer Science or Electrical/Computer Engineering and + 8 years industry experience, or Master’s/Bachelor’s in CS or EE + 10 years industry experience.
• 5+ years of experience in server platform architecture, systems performance engineering, or large-scale infrastructure design for AI/ML, HPC, or performance-sensitive distributed systems.
• Deep understanding of x86 server architecture: CPU microarchitecture basics, cache hierarchies, NUMA, memory controllers/channels, and memory bandwidth vs latency tradeoffs.
• Strong Linux systems knowledge: profiling and performance analysis, scheduling and syscall overheads, memory management behavior, and practical tuning methodology.
• Experience reasoning about high-performance IO paths, including NIC behavior at a systems level, RDMA/RoCE concepts, and NVMe performance characteristics.
• Proven ability to create capacity and performance models and validate them empirically with a rigorous benchmarking plan.
• Experience working directly with vendors/partners to evaluate platforms, drive issue resolution, and influence roadmaps.
• Strong cross-functional communication skills and ability to drive technical decisions through clear tradeoff documents and reviews.
• Familiarity with application and system software (C, C++, Python).

Responsibilities:

• Lead the design and implementation of system-level debugging, validation, and observability platforms.
• Develop automated systems for collecting and analyzing numerical, and execution anomalies.
• Create visualization and analysis tools to enable efficient root-cause investigation.
• Build frameworks for failure classification, regression detection, and anomaly monitoring.
• Extend compilers, runtimes, and programming interfaces to support advanced profiling and instrumentation.
• Improve system bring-up, low-level debug, and validation workflows.
• Partner cross-functionally with compiler, hardware, firmware, runtime, and infrastructure teams.
• Establish best practices for debuggability, reliability, and operational excellence.
• Lead high-impact initiatives.
• Support incident response and drive long-term corrective actions.

Qualifications: 

• Strong proficiency in C++ and Python, with a track record of building reliable, high-performance systems and tooling.
• Demonstrated experience debugging complex hardware/software systems and driving issues to root cause.
• Experience analyzing system-level data structures, execution graphs, or dependency networks for diagnostics and validation.
• Proven ability to design and build intuitive visualization and analysis tools for complex technical data.

• Experience with compiler internals, custom hardware interfaces, or low-level protocol design.

• Strong written and verbal communication skills, with the ability to explain technical concepts to diverse stakeholders.
• Ability to work independently and lead complex technical projects end-to-end.

Preferred Skills & Qualifications

• Familiarity with machine learning training and inference pipelines, especially distributed training and large-model scaling.
• Prior work on high-performance clusters, HPC systems, or custom hardware/software co-design.