Qube Research & Technologies (QRT) is a global quantitative and systematic investment manager, operating in all liquid asset classes across the world. We are a technology and data driven group implementing a scientific approach to investing. Combining data, research, technology and trading expertise has shaped QRT’s collaborative mindset which enables us to solve the most complex challenges. QRT’s culture of innovation continuously drives our ambition to deliver high quality returns for our investors.

QRT's High-Frequency Trading team designs and operates ultra-low-latency systems at global scale.

We’re hiring experienced C++ engineers who are passionate about performance, efficiency, and building highly optimized systems. You’ll work on performance-critical systems with direct impact on live trading outcomes.

Your future role at QRT:

You’ll work across our latency-critical stack - from kernel-level tuning and network optimization to highly efficient C++ components. This role involves close collaboration with our FPGA engineering team as well as our hardware and infrastructure engineers to design end-to-end architectures where every single nanosecond counts.

• Design and optimize C++ systems for trading, market data, and infrastructure
• Profile and fine-tune performance across CPU, cache, and memory layers
• Collaborate with FPGA engineers to integrate hardware and software pathways

Your present skillset:

• 5+ years of experience in performance-critical C++ (C++17 or newer)
• Strong grasp of systems programming, low-level understanding including memory management and CPU's architectures
• Deep familiarity with Linux internals, kernel parameters, and low-level profiling
• Curiosity about hardware, networking, and how systems behave under real load

QRT is an equal opportunity employer. We welcome diversity as essential to our success. QRT empowers employees to work openly and respectfully to achieve collective success. In addition to professional achievement, we are offering initiatives and programs to enable employees to achieve a healthy work-life balance. 

• A key member of the ultra-low-latency team, building and enhancing the next generation trading platform for low-latency and high-frequency execution.
• The platform has been written from the ground up in modern C++23.
• You will be involved in everything from low-level systems programming and networking, to market data, to expressive high-level interfaces.
• We work with QRT's existing systems, with researchers, and with the quantitative developers building & running strategies on the platform.

• 2+ years of experience in low latency Linux development using modern C++, Boost and the standard library
• Experience designing and implementing multithreaded and distributed systems
• Experience in front-office trading desk-aligned role is an advantage
• Good knowledge of distributed network architecture
• Familiar with C++ optimization techniques
• Familiar with Linux / GCC development toolchain
• Knowledge of market data feed handlers and execution gateways highly desirable
• Good team player

About Us:
Founded 20 years ago and headquartered in Chicago, the DV Group of financial services firms has grown to more than 600 people operating throughout North America, Europe and Asia. Since spinning out of a large brokerage firm in 2016, DV Trading has rapidly scaled as an independent proprietary trading firm utilizing its own capital, trading strategies, and risk management methodologies to provide liquidity to worldwide financial markets and hedging opportunities to commodity producers and users. Now, DV group affiliates include two broker dealers, a cryptocurrency market making firm, and a bourgeoning investment adviser.

Role Overview:
We are looking for an exceptional Senior FPGA Engineer to join our semi-systematic equities team. In this role, you will architect and deliver ultra-low-latency FPGA trading systems that drive our competitive edge across global equity and futures exchanges. This position offers the opportunity to lead, innovate, and push the limits of hardware performance in a fast-paced trading environment.

Key Responsibilities:

Technical Leadership

• Lead and mentor a team of FPGA engineers developing next-generation hardware solutions for market making.
• Architect and implement ultra-low-latency trading systems optimized for global equity and futures markets.
• Define and execute the technical vision and roadmap for FPGA-based trading infrastructure.
• Partner closely with quantitative researchers, software developers, and network engineers to deliver integrated, high-performance trading platforms.

System Development

• Design and implement high-throughput FPGA firmware for market data feed handling and order execution.
• Build modular, reusable, and scalable FPGA architectures supporting exchanges such as NYSE, NASDAQ and CBOE.
• Develop robust testing frameworks and automated deployment pipelines to ensure stability and reliability in production.

Required Qualifications:

• 5+ years of hands-on FPGA design and development experience, ideally within high-frequency or market-making systems.
• Expert-level proficiency in SystemVerilog targeting Xilinx platforms.
• Deep understanding of networking and low-level protocols (10G Ethernet, multicast, MAC/PCS layers).
• Proven track record in ultra-low-latency hardware design and performance optimization.

DV is not accepting unsolicited resumes from search firms. Only search firms with valid, written agreements with DV should submit resumes in response to DV’s posted positions. All resumes submitted by search firms to DV via e-mail, the Internet, personal delivery, facsimile, or any other method without a valid written agreement shall be deemed the sole property of DV, and no fee will be paid in the event the candidate is hired by DV. DV is proud to be an equal opportunity employer and committed to creating an inclusive environment for all employees.

Hudson River Trading (HRT) is hiring an AI Researcher to join the HAIL team. HAIL (HRT AI Labs) is the team at HRT responsible for developing and maintaining our most powerful models, which are used by our trading teams to drive a significant fraction of our trading. We are building and deploying "foundation models for markets", that ingest and train on vast amounts of market data, to make predictions about future market state. We are seeking experienced AI researchers to join our team to accelerate our efforts.

Researchers have great independence to pursue the research directions they think would be most impactful as part of a small focused team with minimal bureaucracy. They are enabled by state-of-the-art research clusters with very high GPU-to-researcher ratios, and supported by excellent engineering, hardware, and systems teams to realize their vision. Your work will be directly, clearly, highly impactful on the business, and it will be challenging: this is a field with no easy or obvious solutions. You'll be responsible for improving every part of our models: from featurization of data, to architecture design, to training dynamics, to how trading decisions are made.

Qualifications

• Must have two or more years work experience in deep learning research, for any domain: robotics, biology, chemistry, physics, audio, video, etc.
• Experience translating methods between areas of application is highly valued.
• LLM experience is valuable, but not necessary.
• Strong engineering skills valued, especially any of: GPU kernel development, lower-level Pytorch/JAX development, intermediate C++, FPGA/ASIC experience, HPC experience.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. 

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications 

• Superb debug and analytical skills 
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Hudson River Trading (HRT) is seeking a Physical Design Engineer with a broad, versatile skillset to join our growing Hardware team. In this role, you will help deliver performance-critical ASICs and advance our physical design methodologies on leading-edge process nodes.

The Hardware team at HRT builds high-performance compute engines using FPGA and ASIC technology to drive low-latency trading decisions on global markets. We create custom solutions across the full spectrum of speed and sophistication, from bespoke circuits to world-class machine learning accelerators.

Responsibilities

• Drive design-for-test (DFT) methodologies and implementation 
• Contribute to physical implementation, from RTL handoff through GDSII on advanced process nodes 
• Partner on floorplanning and physical optimization for high-performance, latency-critical designs
• Close timing across multiple modes and corners while optimizing power, performance, and area (PPA)
• Diagnose and resolve physical design issues such as timing bottlenecks, congestion, and IR/EM violations
• Build, maintain, and improve repeatable, automated physical design flows
• Develop scripts and tooling to improve productivity, robustness, and insight into design behavior
• Collaborate closely with RTL, architecture, and other hardware engineers to influence design decisions early

Qualifications

• Experience working in high-performance ASIC design environments
• Strong fundamentals in digital logic, circuit design, and process technology
• Familiarity with DFT concepts and testing methodologies
• Strong scripting and automation skills (Python, Tcl, shell), including parsing and analyzing tool outputs
• Ability to design robust methodologies, diagnose complex failures, and improve physical design flows
• Applied use of statistics in analyzing timing, power, or design data (preferred)
• Hands-on experience with static timing analysis and timing closure methodologies
• Expertise using industry-standard physical design and signoff tools (e.g., Innovus, PrimeTime)

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

About the Position

We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you’ll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.

We’re big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That’s why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don’t expect you to know OCaml (we’ll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

About You

• Have 4+ years practical experience in RTL design and verification
• Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following:
  
  • Front-end RTL design and synthesis
  • Back-end physical design
  • Verification (including formal)
• Interested in using software engineering techniques to improve the hardware design process, and experience programming in some high-level languages (Python, C++, Java, Haskell, etc.)
• Fluent in English 

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com. 

Job Title: Hardware Design Engineer

Reports to: Director of Hardware Engineering

Department: Engineering

💼 About the role

We’re seeking an experienced hardware design engineer to expand our cryptographic hardware IP team. You would be joining a mature design team with a proven track record of delivering market leading cryptographic IP, your role would expose you to the latest cryptographic standards and allow you to develop for the latest technologies.

We hope that you have at least 5 years of experience working on hardware design of complex IPs targeted at deployment on latest generation FPGAs, preferably with some experience working with cryptographic and security IPs.

 We have been established since 2018, so you would be directly working with the founders and inventors of this deep tech startup. The technology is already a couple of years in the making, its feasibility having been established, funding secured, and it has a clear path to market. This is a great opportunity for career progression and to get a head start in a rapidly expanding segment of the technology industry.

⚒️ What you’ll be doing

• Design and implementation of hardware IP blocks and subsystems.
• Tailoring implementations to FPGAs
• Working with verification engineers to create verification and test plans.
• Creation of reliable, reusable and excellently structured hardware design flows.
• Providing feedback to architects on feasibility of implementation and specification quality.
• Ensuring clean lint and implementation reports for IP blocks and subsystems.

🎯 Required Skills And Qualifications

• A commitment to high quality engineering in all areas of their work, including advocating for the best long-term solutions over the easiest or quickest.
• Optimising designs for both area and performance in FPGA technologies.  
• Experience building hardware IP blocks from scratch, and owning the process from initial specification through to customer delivery.
• Confidence bringing up a design using a basic “designers testbench”.
• Experience with standard commercial EDA Design tooling flows.
• Knowledge of common bus protocols (e.g. AMBA AXI4, AHB).
• Experience building and simulating hardware/software co-designs.
• Confidence in debugging RTL simulations issues.
• Degree or equivalent in Electronics/Computer Science or other related discipline.

🖥️ Specific Technologies You Are Confident Using

• FPGA and emulation experience. We use Xilinx FPGAs extensively for prototyping and hardware/firmware co-development.
• Logical IP design using SystemVerilog.
• Version control using Git.
• Writing System and subsystem level tests in C, using CMake as a build system.
• Confidence using tools like Bash, TCL, CMake and Makefiles safely and sensibly.

👍 Preferred Skills And Qualifications

• Python scripting for flows and automation 
• Experience debugging gate level simulations.
• Knowledge of Industry standard SoC Security Architectures
• Knowledge of tamper resistance and/or power side-channel security countermeasures.
• Experience using Gitlab CI, or otherwise principles of continuous integration and testing.

🏆 Some of the perks of working with us:

• Unparalleled opportunities to learn and accelerated career development.
• A collaborative, team environment with people who truly love what they do.
• Competitive salary and share option scheme.
• Flexible and hybrid working, and a working from home budget.
• Private health insurance for yourself and your family.
• 25 days annual leave (plus bank holidays and two wellness weeks).
• 50% gym membership discount.
• The chance to work with a spirited, smart, and friendly team!

Interested? Apply today to be part of the future of secure hardware! 🚀

About the Position

We are looking to hire an Engineer with experience in both software and hardware design to help us build our FPGA-based applications. 

We're big believers in the ability of tools to make programming faster, more pleasant, and more reliable. We apply these same principles to our FPGA Engineering work, and we’re looking for people who are interested in using programming language technology to improve the process of designing, testing, and validating hardware designs. We use Hardcaml, an OCaml library for succinctly describing hardware in RTL. Hardcaml is tightly integrated into our development environment, so you’ll also gain lots of exposure to the libraries and tools that are foundational to our internal systems. No previous knowledge of Hardcaml is required.

In this role, you’ll work on the ground-up design and implementation of new FPGA applications, and help extend and refine the high-level design and testing tools that we use internally. Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing/integration, but you can also expect to work with some Verilog and C. While you don’t need to have worked with OCaml specifically, a good background in typed programming languages is a plus.

If you’d like to learn more, you can read about our interview process, meet some of our newest hires, or check out our OCaml All The Way Down talk and Programmable Hardware podcast episode.

About You

We don’t expect you to have a background in OCaml, finance, or any other specific field—we’re looking for smart programmers who will approach hardware design with a software engineering mindset. We’re more interested in how you think and learn than what you currently know. You should be:

• A top-notch programmer with a love for technology
• Comfortable with a software programming language
• Intellectually curious, collaborative, and eager to learn
• Humble and unafraid to ask questions and admit mistakes
• Experienced with a Hardware Description (or Construction) language (VHDL, Verilog, Chisel, Pymtl, or other), for both writing and testing hardware designs
• Experienced working with FPGA vendor tools (Vivado or Quartus)
• Experienced with building a working FPGA project through an academic, professional, or personal project
• Interested in learning how to use FPGAs in the context of networking
• Fluent in English

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.

HFT Software Developer – Junior & Senior Levels

About DeepFin Research

DeepFin Research is a proprietary high-frequency trading (HFT) firm powered by cutting-edge Deep Learning (DL) and Deep Reinforcement Learning (DRL). We've brought on teammates from Nvidia, DeepMind, CitSec, Graviton, Tower, Jump, and others, and are aggressively working across cutting edge AI research and traditional quant research methods to monetise our AI generated signals across the global financial markets.

The Role

We are looking for exceptional HFT software engineers to build our HFT trading infrastructure across global finanacial markets, including different asset classes, end-to-end from the ground up. This will include working across connectivity, market data, execution, risk, and building high performance high throughput C++ systems.

Responsibilities

• Design, implement, and optimize ultra-low-latency, zero-allocation trading engines in modern C++.
• Develop and maintain market data handlers and execution gateways utilizing protocols like FIX, OUCH, ITCH, and raw UDP multicast.
• Optimize system critical paths through OS-level tuning, CPU pinning, cache-line optimization, and NUMA-aware programming.
• Interface with hardware-accelerated components, working alongside FPGA engineers to integrate PCIe/DMA data pipelines.
• Implement kernel-bypass networking solutions (e.g., Solarflare OpenOnload, DPDK) to minimize network stack latency.
• Collaborate directly with AI researchers and quantitative traders to deploy complex quantitative models into strict, latency-sensitive production environments.
• Work end-to-end on projects from the ground up – this is not a role to focus on specialised parts of the infrastructure stack, but rather to see projects through end-to-end.

Ideal Candidate Profile

• 1–3 years of experience in low-latency software engineering for Junior candidates; 3–10+ years for Senior candidates.
• Exceptional expertise in C++ with a deep understanding of lock-free data structures, custom memory allocators, and hardware architecture.
• Proven experience building systems in HFT or highly concurrent, real-time computing environments.
• Strong grasp of Linux internals, network programming (TCP/IP, UDP), and performance profiling tools (e.g., perf, VTune).
• Solid understanding of futures markets microstructure; exposure to FX and options markets is a strong plus.
• Entrepreneurial mindset with the communication skills required to thrive in a fast-paced, highly collaborative environment, preferring end-to-end ownership over extreme specialization.

HFT Quantitative Developer

About DeepFin Research

DeepFin Research is a proprietary high-frequency trading (HFT) firm powered by cutting-edge Deep Learning (DL) and Deep Reinforcement Learning (DRL). We've brought on teammates from Nvidia, DeepMind, CitSec, Graviton, Tower, Jump, and others, and are aggressively working across cutting edge AI research and traditional quant research methods to monetise our AI generated signals across the global financial markets.

The Role

We are looking for exceptional quantitative developer with outstanding expertise at the intersection of quantitative research and C++ development to focus both on simulation and productionisation. This will include designing and building simulation across various financial markets, and taking high-frequency and mid-frequency alpha turning it into scalable, production-grade PnL across global exchanges.

Key Responsibilities

• Productionise research models into high-performance C++ systems used for live trading across multiple futures exchanges.
• Integrate and process L3/order-book data at scale, building and maintaining parsers, normalised book structures, and data pipelines.
• Develop and optimise execution logic, order placement strategies, queue-positioning logic, microstructure-aware order types, and latency-sensitive workflows.
• Collaborate closely with quant researchers to understand signals, model assumptions, and expected behaviours, ensuring seamless transition from prototypes into production code.
• Work with infra/engineering teams to deploy, monitor, and refine strategies in live environments; diagnose latency bottlenecks, instability, and performance drift.
• Build and maintain simulation/backtesting tools for microstructure-accurate evaluation of execution behaviour.
• Optional (desirable): support vol surface modelling, options execution logic, and cross-asset HFT monetisation.

Required Experience & Skills

• Must have Experience in HFT market making. 
• Outstanding C++ and Python expertise.
• Experience working with L3 and order-book data, market-data adapters, and high-throughput feed handling.
• Experience productionising HFT or mid-frequency strategies in live environments.
• Understanding of market microstructure: queue dynamics, adverse selection, order types, latency paths, tick-rule details.
• Ability to operate across both research and engineering disciplines: reading model code, understanding signals, and implementing robust production systems.
• Options experience is desirable
• FPGA experience is desirable

Maven is a market-leading proprietary trading firm deploying its own capital across discretionary, systematic, and market-making strategies. Backed by deep expertise in trading, technology, and research, we are relentlessly focused on improving liquidity across global listed derivatives. Through advanced execution and pricing technologies, we improve how financial markets operate.

Overview:

Where technology meets trading, the Maven FPGA team is pushing the bleeding edge of hardware and proprietary designs to maintain and gain advantage in an increasingly competitive environment. With operations in London, New York, Hong Kong and Chicago, we build technology in support of global trading operations across multiple exchanges, asset classes, and trading strategies. Our teams are small and nimble, with a firm commitment to growth, and a strategic view of investment in people, tools, and the necessary platforms to extend our leadership.

The Role:

Within our team, you will work with traders and technologists to seek and exploit opportunities to gain competitive advantage through FPGA systems. By means of reduced latencies, higher throughput, or increased robustness, you will enable the company to increase the efficiency of existing strategies and open up entirely new trading opportunities previously inaccessible. With a number of greenfield projects in scope, candidates who are proactive and self-driven can grow into leadership roles for the firm’s future. Whilst financial experience is a plus, your engineering talents, problem solving abilities, and eagerness to take on new challenges are of significantly higher importance to us.

The skills you will have:

• SystemVerilog
• Source control management
• 5+ years FPGA experience
• Automated verification
• HLS or other DSP flow experience for FPGA
• Comfortable attacking new and unfamiliar problems
• Interest in trading

Things we would like to see but are not essential:

• Python, TCL
• Low latency design
• ASIC
• Network and packet processing
• Financial market data
• Trading systems
• Software development

WHAT WE OFFER

• Competitive compensation 
• Group Pension plan 
• Annual discretionary bonus 
• Fully catered breakfast, lunch and snacks. 
• 25 days’ annual leave
• Informal dress code 
• Private healthcare and life assurance
• Cycle-to-work scheme
• Monthly company events
• Private Gym

Maven is a market-leading proprietary trading firm deploying its own capital across discretionary, systematic, and market-making strategies. Backed by deep expertise in trading, technology, and research, we are relentlessly focused on improving liquidity across global listed derivatives. Through advanced execution and pricing technologies, we improve how financial markets operate.

Working on our trading floor, you will work alongside traders, quant researchers and other developers to help us expand system connectivity to new markets, optimise order execution algorithms, improve our trading strategies and build new automated pricing systems and infrastructure to support the expansion of our options market making business. The work you do will have a direct, regular and highly visible impact on the firm's success.

The skills you will have:

• Excellent C++ (11/14/17/20/23)
• Template programming
• Ultra low latency design
• Performance tuning and analysis
• Good numerical skills
• The ability to solve new and unfamiliar problems quickly and creatively
• An efficient and diligent approach with a strong attention to detail
• Excellent written and verbal communication skills
• An Interest in trading and finance

Things we would like to see but are not essential:

• Knowledge of financial markets & securities (particularly futures and options)
• Experience in the other programming languages: Python, C# or JavaScript
• Experience with NoSQL and time-series databases
• Knowledge of multiple derivative exchange platforms
• Network communication protocols UDP and TCP
• Network acceleration using proprietary drivers and kernel bypass
• Understanding of and optimisation for modern Intel architecture

If you don’t meet every requirement listed, we still encourage you to apply. We value potential and are excited to see what you can bring to the role.

What you will be doing with us:

• Full lifecycle of software development for market making, working alongside traders and developers in other teams, such as FPGA, data analytics and UI developers
• Developing low latency exchange connectivity components for new markets

We pride ourselves on being able to rapidly deliver well-engineered software into production. You will be able to see the impact of your work immediately and will be in a unique position to have a direct impact on trading revenue. We make extensive use of automated testing and peer code review to ensure quality and maintainability while keeping time-to-market short.

WHAT WE CAN OFFER YOU

• Competitive compensation 
• Group Pension plan 
• Annual discretionary bonus 
• Fully catered breakfast, lunch and snacks
• 25 days’ annual leave
• Informal dress code 
• Private healthcare and life assurance
• Cycle-to-work scheme
• Monthly company events
• Private Gym