Team Description:

We build the electrical systems that make high-bandwidth brain–computer interfaces possible. This includes neural signal acquisition and stimulation to wireless power delivery, embedded processing, and system integration—all within devices small enough to be implanted in the human body and efficient enough to operate under strict thermal and power constraints. Our work sits at the intersection of analog, RF, digital, and biological systems. Many problems in this space do not present clean abstractions or clear failure modes. Success often depends on careful measurement, iteration, and engineering judgment across multiple interacting systems.

Job Description and Responsibilities:

We are looking for an experienced, hands-on electrical engineer for implant electronics board design, integration with our custom chips, testing, and quality control. You will have the opportunity to contribute to advanced projects, not only work on incremental changes, and be an integral member of a small, fast-moving team. You will be working on all phases of board design (part selection, schematic design, layout, and bring-up) as well as collaborating closely with chip designers, firmware engineers, mechanical engineers, and microfabrication experts for system integration.

• Utilize electrical engineering fundamentals and best system design practices to build on your ability to deliver high-performant, reliable, and manufacturable extremely size-constraint systems
• Gain understanding of all phases of system and board design, from system definition to part selection, schematic design, layout, bring up, and design verification
• Contribute to R&D investigations and experiments to demonstrate feasibility of new technology for the implant and the charger
• Gain experience working cross functionally to ensure successful systems integration
• Contribute to system improvements that decrease latency and increase battery life, reliability, and safety
• Develop ability to design and deploy systems for implant-charger hardware in the loop testing, and manufacturing line quality control

Required Qualifications: 

• Strong EE fundamentals
• Experience designing PCBs for low power and size constrained applications
• Experience with PCB CAD tools (Altium, Eagle, KiCad, Allegro)
• Experience with sensors, power management, and signal/power integrity
• Comfortable with common communication protocols (SPI, UART, I2C, etc.)
• Comfortable with lab equipment (oscilloscope, VNA, etc.)
• Basic C and Python programming skills

Preferred Qualifications:

• Experience with firmware development for embedded systems (C/C++)
• Experience with wireless systems (BLE, WIFI, Zigbee)
• Experience building and bringing-up MCUs or FPGA
• Proficiency with ME CAD tools (Solidworks, AutoCAD)
• Experience with analog circuit design

Expected Compensation:

The anticipated hourly rate for this position is listed below.

California Hourly Flat Rate:
$35/Hr USD

Team Description:

Join the Brain Interfaces Embedded Systems Team and be part of an elite team of engineers working on high-performance, safety-critical embedded systems for the next-generation brain-computer interfaces. You will have the opportunity to work closely with chip designers, electrical engineers, and software engineers on a small, fast-moving team.

Job Description and Responsibilities: 

We are looking for experienced, hands-on engineers who are interested in exploring what's possible in highly powered and latency-constrained environments. Firmware is the kernel of operation for the implant, and you have the chance to define and implement features that have a significant impact on the product’s capabilities. As an Embedded Software Engineer, you will be expected to:

• Own complex challenges from definition to solution
• Utilize your ability to work cross functionally to deliver safety critical systems while considering power, radio, and thermal requirements
• Take ownership of products and/or core features; from planning and design to execution and testing
• Build on your fundamental understanding of hardware while contributing to bare-metal firmware
• Embrace a fast-paced iterative environment that prioritizes shipping manufacturable solutions 

Note: The team is hiring embedded engineers at all levels, both junior and senior. What matters most is evidence of exceptional abilities and a drive to succeed.

Required Qualifications: 

• Bachelor’s degree in computer science, electrical engineering, related field, or equivalent experience 
• 1+ years of experience with embedded systems (including internships)
• Proficient in embedded C or Rust
• Ability to design bare-metal embedded systems in highly constrained environments
• Strong Electrical Engineering fundamentals 
• Signal processing fundamentals 
• You find enormous challenges exciting and enjoy discovering and defining problems as much as solving them
• You deliver. You may enjoy thoughtful conversations about problems and perfecting design, but in the end, you know that delivering reliable manufacturable solutions matters
• You are a cross-disciplinary team member. You are excited to work with and learn from chip designers to neuroscientists

Preferred Qualifications: 

• Experience with embedded stacks for ARM cores
• Experience with safety-critical systems
• Experience with FPGA development and testing
• Experience with RF, BLE, TCP/IP stacks from a practical embedded perspective
• Prior work or experience with applied cryptography and embedded systems security

Team Description:

The Surgery & Robotics Hardware Team is looking for Electrical Engineers who want to advance the future of healthcare solutions with technology. At Neuralink we recognize that increasing healthcare costs, lack of access, and insufficient numbers of neurosurgeons globally require new approaches to enable greater access to our devices. To address these challenges we design fully autonomous robotics systems, human assistive surgical tools, and design entire surgical suites in order to provide better experiences for our customers.

Our team works on our surgical robot system which aims to fully automate the implantation of the Neuralink implant. We design and integrate multi-axis robotic arms, perception systems including custom imaging hardware, optical coherence tomography tissue imaging, power electronics, and safety systems such as 3D spatial mapping/object avoidance sensors. Robotics is part of a larger system of tools we work on. For example, using pre-op MRI scans we generate patient anatomy data that we later use in surgery to register precise surgery site locations. 

In addition to research and development of modern surgical technology, we also are responsible for bringing these technologies to market. We perform full lifecycle testing for all devices we design and ultimately manufacture them for use in human surgeries. To date, our designs have served over 20 individuals, and in the coming years our designs will serve thousands of individuals who wish to use our implant technology.

Job Description and Responsibilities:

As an Electrical Engineer on the Surgery & Robot Hardware Team, you will be expected to design, verify, and oversee the transition to production of a variety of custom electronics systems.  This role offers substantial autonomy and the exciting opportunity to own creative decisions and execute on new, impactful projects such as robotics stage designs, motor drives and controls, custom camera designs, manufacturing automation, and the firmware that enables all of these devices.

Required Qualifications: 

• Bachelor’s degree in Electrical Engineering or a related field or equivalent experience
• Professional experience delivering on all phases of electronics design (requirements, part selection, schematic, layout, manufacturing, test)
• Demonstrated depth in at least one of the following:
  • Power electronics: experience designing custom power conversion, distribution, eFusing, and battery management systems in the low-to-medium (1W-2kW) range
  • FPGA hardware design for time sensitive systems such as image processing, high-speed data acquisition, or real time networking. Professional experience in FPGA selection, RTL development, digital signal processing theory and techniques, and hardware design to interface high speed physical layer devices via PCIe, MIPI, SLVS-ec, LVDS, etc
  • Manufacturing automation design: professional experience architecting and implementing manufacturing automation solutions for products that currently ship at the scale of 1000’s+
• Practical electronics design knowledge including designing for EMC, ESD, thermals and packaging

Preferred Qualifications: 

• A portfolio showcasing your hardware designs 
• Demonstrable experience developing electronics for safety critical systems such as medical devices, aerospace, automotive, or military
• Demonstrable experience shipping code in one of the following languages: C, C++, Python, or Rust
• Altium experience

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As a Digital IC Design Engineer Intern, your responsibilities will include:

• Micro-architecture design and RTL implementation of: 
• Low-power digital signal processors
• Low-power general-purpose hardware accelerators
• Low-power graphics processing units
• Low-power radio MAC/PHY
• Low-power serial link MAC/PHY
• Design and implementation of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
• Complex system modeling for energy and performance benchmarks
• Workload analysis and modeling
• Leveraging architecture-level design trade-offs with process technology and workload type
• Balancing energy efficiency and performance under manufacturing process variation 
• Complex system-on-chip verification
• Behavioral level modeling and model equivalence check
• FPGA emulation
• Analog mixed-signal co-simulation
• Design for testability 
• Collaboration on silicon bring-up tests with silicon validation engineers 

Required Qualifications:

• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• 2+ years of experience in digital design
• Proficient in SystemVerilog, C/C++, Python
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications:

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++, or UVM 
• Experience automating tool flows
• Experience with embedded design
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization
• Experience designing PCBs or writing firmware.

Expected Compensation:

The anticipated hourly rate for this position is listed below.

California Hourly Flat Rate:
$35/Hr USD

Principal Embedded SW/FW Engineer (Bringup)

Salary $241,100 - $326,100 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Senior Embedded SW/FW Engineer (Bringup)

Salary $156,500 - $211,700 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Senior Post Silicon Validation Engineer (Bringup)

Salary $156,500 - $211,700 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Principal Post Silicon Validation Engineer (Bringup)

Salary $241,100 - $326,100 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

This role entails design and development of scalable infrastructure and software for the verification of high performance CPUs going into industry leading AI/ML architecture. The successful candidate will be responsible for development and automation of many aspects of the verification environment. The person coming into this role will have opportunities such as: writing low-level RISC-V assembly, building complex low-latency multithreaded testbenches, database programming, software testing and release automation, verilog coding and optimization of CPU components, and contributing to open source projects in the RISC-V ecosystem.

This role is on site, based out of Santa Clara, CA or Austin, TX.

This is for our Fall 2026 Semester

Responsibilities:

• Build software and scripts for high performance simulation and emulation of CPUs
• Improve verilog for optimal simulation performance and fpga emulation synthesis
• Maintain and enhance the Git infrastructure to support CI/CD, nightly regressions across multiple development platforms
• Build software tools and scripts for design flow automation

Experience & Qualifications:

• Currently working towards a Bachelors program
• Strong programming skills. C++, Python, SystemVerilog preferred.
• Solid experience with the Linux operating system
• Experience with version control. Git preferred.
• Interest in CPUs, hardware design, and/or programming
• Willing to learn and adapt

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

FPGAs and ASICs are critical pieces of our technology stack. We are looking for talented hardware developers to architect and design complex systems on a highly collaborative global team. In this role, you'll identify efficient ways to perform on-the-fly transformations of market data and implement models with complex data structures in RTL. Deep knowledge of SystemVerilog, FPGA internals and/or ASIC primitives, computer architecture, and vendor tool suites are essential to succeeding in this role. Expertise in networking protocols, CPU design, and/or machine learning accelerators is a big plus. No financial experience is necessary.

Responsibilities

• Collaborate with a cross-functional team to develop and deploy custom FPGA and/or ASIC solutions for a wide range of trading applications
• Investigate new technologies and tools
• Contribute to a nimble hardware development tech stack

Qualifications

• Ability to describe hardware designs at a high level, low level, or anywhere in between
• Brilliant design, optimization, debugging and problem solving skills
• Professional experience (2+ years) in RTL design for FPGA or ASIC
• Expert SystemVerilog development skills with a thorough understanding of the language 
• Expert on low level FPGA or ASIC architectures, with a deep understanding of what makes them "tick"
• Skilled in network communications, processing pipelines, and/or machine learning
• Working knowledge of Python and/or C++
• Comfortable in a Linux environment
• Strong verification experience
• Familiarity with AMD Vivado is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

Hudson River Trading (HRT) is seeking a Physical Design Engineer with a broad, versatile skillset to join our growing Hardware team. In this role, you will help deliver performance-critical ASICs and advance our physical design methodologies on leading-edge process nodes.

The Hardware team at HRT builds high-performance compute engines using FPGA and ASIC technology to drive low-latency trading decisions on global markets. We create custom solutions across the full spectrum of speed and sophistication, from bespoke circuits to world-class machine learning accelerators.

Responsibilities

• Drive design-for-test (DFT) methodologies and implementation 
• Contribute to physical implementation, from RTL handoff through GDSII on advanced process nodes 
• Partner on floorplanning and physical optimization for high-performance, latency-critical designs
• Close timing across multiple modes and corners while optimizing power, performance, and area (PPA)
• Diagnose and resolve physical design issues such as timing bottlenecks, congestion, and IR/EM violations
• Build, maintain, and improve repeatable, automated physical design flows
• Develop scripts and tooling to improve productivity, robustness, and insight into design behavior
• Collaborate closely with RTL, architecture, and other hardware engineers to influence design decisions early

Qualifications

• Experience working in high-performance ASIC design environments
• Strong fundamentals in digital logic, circuit design, and process technology
• Familiarity with DFT concepts and testing methodologies
• Strong scripting and automation skills (Python, Tcl, shell), including parsing and analyzing tool outputs
• Ability to design robust methodologies, diagnose complex failures, and improve physical design flows
• Applied use of statistics in analyzing timing, power, or design data (preferred)
• Hands-on experience with static timing analysis and timing closure methodologies
• Expertise using industry-standard physical design and signoff tools (e.g., Innovus, PrimeTime)

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications 

• Superb debug and analytical skills 
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

Austin is home to Optiver’s hardware research, development, and manufacturing group. We build some of the world’s most competitive trading hardware—high-speed, high-density systems that push the limits of performance, reliability, and manufacturability.

We’re growing fast and looking for a Manufacturing Test Engineer focused on PCBA test development and deployment. You’ll own board-level test solutions from early prototypes through volume production—building fixtures, developing automation, driving debug, and partnering closely with contract manufacturers and our internal EE/ME/FPGA/firmware teams.

We’re a small, highly technical team, and this role comes with real autonomy: you’ll have the runway to improve how we do test, raise the bar on factory readiness, and build scalable processes as our hardware footprint grows.

Who we are

Optiver is a tech-driven trading firm and leading global market maker. As one of the oldest market making institutions, we are a trusted partner of 70+ exchanges across the globe. Our mission is to constantly improve the market by injecting liquidity, providing accurate pricing, increasing transparency and acting as a stabilizing force no matter the market conditions. With a focus on continuous improvement, we participate in the safeguarding of healthy and efficient markets for everyone who participates.

Based in ‘The Domain’ neighborhood, Optiver’s Austin office serves as the firm’s innovation nucleus, with a strong focus on quantitative research, software and hardware engineering initiatives. With tech innovation an integral part of our core business, the booming city proved an ideal backdrop for our heavy investment into machine learning, research infrastructure and big data computing. What’s more, with world-class music, food and art scenes, as well as countless scenic outdoor activities, the quality of life for Austin Optiverians is second to none.

What you’ll do

• Own PCBA manufacturing test strategy across the product lifecycle:
• EVT/DVT/PVT → ramp → sustaining
• coverage definition, limits/thresholds, logging, and yield monitoring
• Design and build PCBA test fixtures spanning:
• ICT & Functional verification test (FVT)
• Burn-in / reliability screening
• Final assembly tests (FATP)
• System interoperability testing
• Develop automated test software with strong emphasis on Python scripting, maintainability, and scalability
• Partner with contract manufacturers to deploy tests on the line, train vendor teams, and drive continuous improvement.
• Drive DFT/DFM feedback into design reviews with EE and ME teams
• Define and maintain test documentation:
• Test plans, work instructions, golden unit strategy, calibration/maintenance procedures, and acceptance criteria.
• Use modern tooling (including AI-assisted workflows where helpful) to speed up debug, log triage, and documentation—without compromising repeatability and traceability.
• Travel periodically to supplier sites to support NPI builds, line bring-up, and ramp

Who you are

Requirements

• BS in Electrical Engineering, Computer Engineering, or related discipline.
• 3+ years of industry experience
• Strong Python skills: automation, hardware I/O, parsing logs, data analysis, packaging/CI practices.
• Ability to understand register maps and leverage HALs for creation of test scripts
• Proficient ECAD skills to develop schematics and oversee layout work: Altium, Mentor Graphics, Cadence or equivalent.
• Hands-on experience developing and deploying manufacturing PCBA tests in a production environment.
• Comfortable with hardware debug using scopes, DMMs, logic analyzers, protocol analyzers; strong troubleshooting instincts.
• Experience working with contract manufacturers and external vendor engineering teams, including clear communication and escalation management.

Nice to have

• Familiarity with FPGA prototyping and basic RTL concepts (enough to support debug/bring-up and test hooks).
• Familiarity with C and/or C++ for embedded firmware development
• Experience with high-speed digital board debug (clocking, SERDES links, power sequencing, SI/PI-related failure modes).
• Solidworks familiarity.

What you’ll get:

• Work alongside best-in-class professionals from over 40 different countries.
• Performance based bonus structure that is unmatched anywhere in the industry. We combine our profits across desks, teams and offices into a global profit pool fostering a truly collaborative environment to work in.
• Ownership over initiatives that directly solve business problems.  

Alongside this you will get great other benefits such as 25 paid vacation days and market holidays, fully paid health insurance, daily breakfast and lunch, training opportunities, 401(k) match up to 50% and charitable match opportunities, regular social events and clubs, and many more.

At Optiver, we are committed to creating a diverse and inclusive environment of mutual respect. Optiver recruits, employs, trains, compensates and promotes regardless of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics. 

Optiver’s hardware research, development, and manufacturing team, based in Austin, builds some of the world’s fastest and most competitive trading systems. As we continue to grow, we’re looking for a software engineer to help develop the OS and software that powers our custom hardware.

This role spans everything from low-level hardware integration to collaborating with infrastructure teams that manage production systems and traders who configure them to fit their specific needs. While we primarily use Python and Linux, you’ll also encounter a diverse tech stack including TCL, C, C++, ASM, VHDL, and DSLs across platforms from x64 servers to embedded cores.

What you’ll do:

As Software Engineer, your key responsibilities include:

• Designing and maintaining the OS and software stack behind our trading hardware
• Building and supporting Python-based interface layers to control and monitor hardware systems
• Developing software for STM processors embedded on prototype boards
• Managing and supporting a fleet of hardware systems in a live production environment
• Collaborating closely with hardware, infrastructure, and trading teams to ensure seamless system performance
• Contributing to infrastructure automation and transitioning into embedded development and low-level hardware logic over time

What you’ll get:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• Strong foundation in computer science fundamentals and hardware systems
• Proficiency in Python, including familiarity with relevant libraries and APIs
• Experience writing software in C/C++
• Creative problem-solving skills at the system level
• Ability to collaborate with developers and researchers

Nice to have:

• Experience with low-level hardware/software interactions (drivers, buses, pins, registers, etc.)
• Ability to read and interpret datasheets and electrical engineering schematics
• Familiarity with devices and drivers in Linux
• Experience with FPGA design using VHDL/Verilog and the Vivado suite of tools
• Knowledge of communication protocols, especially Ethernet
• Exposure to network equipment operating systems like Cisco IOS, Arista EOS, or Juniper MOS
• Experience working with high-performance trading network hardware (both packet- and circuit-switched)

Who we are:

At Optiver, our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency, and stabilising the market no matter the conditions. With a focus on continuous improvement, we prioritise safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

This role will be on-site 5 days a week in NW Austin.

Scope  

This role will be on-site 5 days a week in NW Austin. 

As the Sr Multimedia System Architect at Ambiq, you will drive the architectural definition of various aspects of Ambiq’s low-power SoCs, with a specific focus on multimedia technologies, including graphics, display, video, imaging, and AI. 

This is a critical function at Ambiq that supports the delivery of the world’s lowest-power electronic devices, enabling ubiquitous AI at the edge. This is a cross-functional position working with software and hardware engineering teams, applications engineering, and field teams to ensure alignment to product requirements, logical and physical design constraints, power and performance targets, and overall system architecture. This role will encompass high-level architectural specification, low-level microarchitecture, process-node-dependent analysis, power/performance modeling, and use-case definition. 

Specific Responsibilities 

• Architecture specifications, including flow diagrams/sequences, power/performance models, and pseudocode 
• Customer interaction is needed to ensure alignment on key multimedia features and competitive product positioning  
• Microarchitecture specifications (as applicable) and support to enable software and hardware design 
• Support for use case and test case development 
• Integration specifications to support system interfaces and external power management requirements/interfaces 
• Work with the FPGA team to bring up critical multimedia features 
• Work with software architecture to define multimedia flows, APIs, and hardware abstraction layers 
• Work with the physical design team to ensure robust/optimal implementation 
• Work with the design team to debug issues using RTL and gate-level simulation 

Expectations for a successful candidate are as follows: 

• Work with Ambiq’s Marketing, Advanced Development, architecture, and engineering teams to drive development of new ultra-low power multimedia architectures on Ambiq Micro’s technology and product roadmaps 
• Develop high-level specifications and drive power/performance modeling and analysis 
• Analyze low-power multimedia technology and applications to identify opportunities for extending Ambiq’s low-power leadership 
• Define Ambiq’s multimedia and AI technology roadmap, including external and internal IP assessment, definition, and integration 
• Work with the engineering teams to transition the architecture specification into Ambiq Micro’s products 
• Work with systems, solutions, and software teams to ensure robust interfaces and support key product use cases 
• Support post-silicon analysis and efficient delivery of multimedia functionality to customers for mass production 

Requirements 

The candidate should be comfortable with independent specification, analysis, and development from high-level concepts through design and validation, as well as collaborative development with software and hardware engineering. A deep knowledge of graphics accelerators, graphics processing, display controllers and panel interfaces, image signal processors, video encoding/decoding, image sensors, or neural network accelerators specifically targeting wearable, IoT and mobile systems are critical, along with specific experience delivering low-power architectures to market. A working knowledge of SoC architecture, fabric/interconnect technologies, power management, and advanced process nodes is preferred. The candidate should be comfortable with complete system dataflows and modeling to guide hardware and software analysis and development. 

Specific Experience 

• Minimum of 8 years of graphics, display, video, imaging or neural networks or similar architecture and design experience targeting wearable/IoT and mobile products 
• Experience developing novel multimedia architectures from idea to specification to design to post-silicon validation 
• Working knowledge of low-power modern mobile consumer electronic systems and embedded graphics, imaging or neural network processing required 
• Experience in embedded display technologies and low-power interfaces required 
• Experience in advanced process technologies is highly desirable 
• BS in Electrical Engineering, Computer Engineering or Computer Science (must have) 
• MS or PhD (preferred) 
• Individual contributor role, but some management/team lead experience is nice-to-have 
• Must have experience creating architectural specifications for System-on-Chip or similar complex hardware devices 
• Must communicate well (verbal and written) 

Must be currently authorized to work in the United States for any employer. We do not sponsor or take over sponsorship of employment visas (now or in the future) for this role.

This role will be on-site 5 days a week in NW Austin.

Scope

The Sr Director of System Architecture will be responsible as the lead architect for developing next-generation ultra-low-power, AI-based SoC architectures for future Ambiq products. The candidate will own the development and coordination of new product architectures with the Marketing, Advanced Development, and Engineering teams. This position will report directly to the VP of Architecture. Areas of interest include: low-power embedded microprocessor and microcontroller-based System on Chip (SoC), interconnect technologies, memory technologies and topologies, clocking, power management, as well as preferred familiarity with 2D and 3D graphics accelerators and display controller technologies, video and image processing, and Neural Network processors/accelerators/NPUs. The candidate will have sufficient experience with system-level design, hardware/software partitioning, power, and performance modeling/tradeoffs.

Expectations for a successful candidate are as follows:

• Work with Ambiq’s Marketing, Advanced Development, architecture, and engineering teams to drive development of new ultra-low power AI System on Chip (SoC) architectures on Ambiq Micro’s technology and product roadmaps
• Develop high-level specifications and drive power/performance modeling and analysis
• Analyze low power interconnect, memory and hardware accelerator technologies and applications to identify opportunities for extending Ambiq’s low power leadership
• Support definition of Ambiq’s technology roadmap including external and internal IP assessment, definition, and integration
• Work with the engineering teams to transition architecture specification into Ambiq Micro’s products
• Work with systems, solutions, and software teams to ensure robust interfaces and support key product use cases
• Support post-silicon analysis and efficient delivery of Ambiq products to customers for mass production

Specific Responsibilities

As the Sr Director of System Architecture at Ambiq, you will lead architecture definition of various Ambiq low power AI SoC’s from initial concept to mass production.

This is a critical functional at Ambiq to support delivering the world’s lowest power electronic devices to enable ubiquitous AI at the edge. This is a cross-functional position working with software and hardware engineering teams, applications engineering and field teams to ensure alignment to product requirements, logical and physical design constraints, power and performance targets and overall system architecture. This role will encompass high level architecture specification, low level microarchitecture, process node dependent analysis, power/performance modeling, analysis, and use case definition.

• Architecture specifications including flow diagrams/sequences, power/performance models and pseudocode
• Customer interaction as needed to ensure alignment on key features and competitive product positioning
• Microarchitecture specifications (as applicable) and support to enable software and hardware design
• Support for use case and test case development
• Integration specifications to support system interfaces and external power management requirements/interfaces
• Work with FPGA team to bringup critical SoC features
• Work with software architecture to define flows, APIs and hardware abstraction layers
• Work with physical design team to ensure robust/optimal implementation
• Work with design team to debug issues using RTL and gate level simulation

Education and Experience:

The candidate should be comfortable with independent specification, analysis and development from high level concepts through design and validation as well as collaborative development with software and hardware engineering.  A deep knowledge of embedded systems and microprocessor/microcontroller based AI System on Chip (SoC) specifically targeting wearable, IoT and mobile systems is critical along with specific experience delivering low power architectures to market. A working knowledge of SoC architecture, fabric/interconnect technologies, power management and advanced process nodes is required. Additionally, experience with wireless technologies and SoCs specifically Bluetooth, WiFi, NFC and GPS is preferred. The candidate should be comfortable with full system dataflows and modeling to guide hardware and software analysis and development.

Specific Experience

• Minimum of 15 years of microprocessor/microcontroller based System on Chip or similar architecture and design experience targeting wearable/IoT and mobile products
• Experience developing novel low power architectures from idea to specification to design to post-silicon validation
• Working knowledge of low power modern mobile consumer electronic systems required
• Experience in advanced process node technologies highly desirable
• BS in Electrical Engineering, Computer Engineering or Computer Science (must have)
• MS or PhD (strongly preferred)
• Individual contributor role but strong technical and team leadership experience is desired.
• Must have experience creating architectural specifications for System-on-Chip or similar complex hardware devices
• Must communicate well (verbal and written)

**Must be currently authorized to work in the United States for any employer. We do not sponsor or take over sponsorship of employment visas (now or in the future) for this role.

Virtu is a leading financial firm that leverages cutting edge technology to deliver liquidity to the global markets and innovative, transparent trading solutions to our clients. As a market maker, Virtu provides deep liquidity that helps to create more efficient markets around the world. Our market structure expertise, broad diversification, and execution technology enables us to provide competitive bids and offers in over 19,000 securities, at over 235 venues, in 36 countries worldwide.

THE ROLE

Virtu's Hardware team builds custom FPGA solutions and infrastructure that power our competitive edge in ultra low latency trading. Our Hardware Platform Engineers are responsible for deploying, maintaining, and optimizing hardware platforms while developing software applications to control and monitor production systems. As a member of the team you will take a lead role in:

• Testing and troubleshooting hardware equipment
• Defining and implementing hardware platform deployment plans 
• Developing and maintaining applications to control/monitor custom hardware platforms
• Researching and evaluating hardware providers, features, and capabilities 

About the Team

AVRIDE is an autonomous driving company with the mission to make transportation safer and more efficient
through cutting-edge technology. We hold a unique position in the market, developing self-driving taxis and
delivery robots. Our delivery robot division already has production in the US and Japan. Our team consists of
highly talented engineers with extensive expertise. Joining us means diving into a startup atmosphere and
making a significant impact on the company's results and the autonomous industry as a whole.

About the Role

As a Software Engineer at Avride, you will design and develop advanced firmware and drivers for LiDAR, motor 
control, and robotics systems. You’ll work with FPGAs, MCUs, and embedded platforms to build reliable,
high-performance solutions that power our autonomous technologies. This role combines deep expertise in low-level
programming, DSP optimization, and embedded systems integration, with hands-on testing and collaboration
across cross-functional teams to deliver cutting-edge solutions.

What You'll Do

• Design and develop firmware for LiDAR systems using SystemVerilog, optimize (digital signal processing) DSP algorithms to ensure high performance and reliability.
• Design and develop firmware for motor control on field programmable gate arrays (FPGAs) and microcontroller units (MCUs), provide calibration for optimal power consumption and stability.
• Develop drivers and software for CAN-bus gateway on MCU ensuring seamless communication between devices and systems.
• Develop drivers and software for uart, lin, ethernet peripheral devices and sensors for robotics systems.
• Design, implement, and maintain software for testing stands, utilizing Python and C++ to automate testing processes and improve efficiency.
• Collaborate with cross-functional teams to integrate firmware and software components into embedded systems.
• Perform testing, debugging, and optimization to ensure the quality and reliability of embedded solutions. Mostly using various measuring equipment.
• Provide technical support and assistance to internal teams and external partners as needed.

What You'll Need

• Bachelor's degree in Applied Mathematics, Electrical Engineering, Radio-technology or a related field. Foreign equivalent is accepted. 
• At least 12 years of experience in software engineering or similar. Alternatively, Master’s Degree in Applied Mathematics, Electrical Engineering, Radio-technology or equivalent plus at least 5 years of progressive work experience in software engineering. 
• Strong programming skills in Python, C++, and SystemVerilog, experience with MCU (STM, NXP) and FPGA (Xilinx, Intel, Lattice) programming. 
• Proven experience in firmware development for data processing and hardware control systems. 
• Knowledge of DSP concepts like FIR/IIR filters, FFT, convolution, signal reconstruction.
• Strong programming skills in Python, C++, and experience with MCU programming.
• Familiarity with CAN-bus communication protocols, Ethernet, spi, i2c and experience developing drivers for this peripheral.
• Solid understanding of embedded systems design principles, real-time operating systems, experience with hardware-software co-design and integration.
• Excellent problem-solving skills and attention to detail.
• Effective communication skills and the ability to work both independently and collaboratively in a team environment.

Efficient is looking for a seasoned Design Verification & Emulation Manager to staff, lead and scale our verification and emulation organization which is part of our newly formed HW engineering organization. This is a high-impact leadership role responsible for ensuring silicon correctness and system-level readiness across multiple industry defining product lines. You will own the verification strategy from block-level to full-chip, drive emulation-based validation for early software enablement, and build a world-class team of verification and emulation engineers.

This role combines deep technical expertise with strong people leadership and program execution skills, and is ideal for someone who thrives at the intersection of architecture, verification methodology, hardware-software integration, and team building. This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.  Join our team and help us shape the future of computing at the edge and beyond! 

Key Responsibilities 

• Define end-to-end verification strategy from block-level through full-chip simulation to emulation and prototyping
• Own UVM-based methodology, including constrained-random, coverage-driven closure, assertions, and formal verification adoption
• Drive emulation platform strategy — platform selection, capacity planning, compilation flows, and multi-project scheduling
• Enable system-level validation on emulation — processor boot, OS bring-up, firmware execution, and IO exercising
• Deliver pre-silicon platforms for early software development in partnership with firmware and software teams
• Establish hybrid simulation-emulation methodologies using transactor-based interfaces to maximize both environments
• Own functional coverage models and sign-off criteria, driving closure across simulation and emulation combined
• Lead debug and root cause analysis across simulation and emulation, driving cross-functional bug resolution
• Manage verification dashboards, bug tracking, and regression health to provide clear visibility to program leadership
• Build, mentor, and scale a high-performing team of verification and emulation engineers
• Drive verification schedules and risk mitigation aligned with chip program milestones and tapeout readiness
• Represent verification and emulation in tapeout readiness reviews and program-level decision forums
• Collaborate cross-functionally with Compiler Team, RTL design, architecture, DFT, physical design, and post-silicon teams
• Manage emulation lab infrastructure, including hardware resources, licensing, and vendor relationships
• Evaluate and adopt new EDA tools and methodologies, including AI/ML-assisted verification techniques.
• Define right DV  mix for in-house  vs outsourcing to 3rd party vendors. Coordinate 3rd party vendor resources towards achieving project goals.

Required Qualifications & Experience 

• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. PhD is a plus.
• Experience: 12+ years of progressive experience in ASIC/SoC design verification, with at least 3–5 years in a management or senior technical leadership role overseeing both verification and emulation functions.
• Verification Methodology: Deep expertise in UVM, constrained-random verification, functional coverage, assertions (SVA), and simulation-based debug. Strong understanding of formal verification techniques.
• Emulation Platforms: Hands-on experience with at least one major emulation platform (Palladium, ZeBu, or Veloce) and familiarity with FPGA prototyping flows.
• Languages & Tools: Strong proficiency in SystemVerilog, Verilog, and C/C++ for testbench and reference model development. Experience with Python, Tcl, and scripting for flow automation.
• SoC Architecture: Solid understanding of modern SoC architectures — processors (ARM, RISC-V), cache coherency, interconnects (AMBA AXI/ACE/CHI), memory subsystems, and common peripherals.
• Leadership: Demonstrated ability to build, mentor, and manage verification teams of 10+ engineers. Experience hiring, developing talent, and scaling teams.
• Execution: Strong track record of driving verification closure and tapeout sign-off on complex designs (multi-million gate, multi-clock domain, multi-power domain).

Preferred Qualification

• Experience with portable stimulus standard (PSS / Accellera) for verification reuse across simulation and emulation.
• Background in power-aware verification (UPF/CPF-based) and low-power design verification challenges.
• Experience with AI/ML-assisted verification techniques (e.g., intelligent coverage convergence, ML-driven regression optimization).

We offer a competitive salary for this role, generally ranging from $210,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

This role will be on-site 5 days a week in NW Austin.

Scope  

As a member of the Security team at Ambiq, the Embedded Software Engineer - Security will participate in extending and supporting Ambiq’s Secure Bootrom/Bootloader and SDK for the Apollo SoC  and emulation platforms. This role will work within our global MCU software development team. It will work closely with the architecture team and the local MCU SoC design team, focusing on MCU software development and test activities. A successful candidate should be a fast-learning, result-driven, and self-motivated team player with an “always learning” mindset. They should possess an inquiring spirit and be comfortable working in a lab environment, with the ability to execute hands-on debugging for embedded systems. The candidate will be involved in extending each of these to cover new MCU members of the family as they become available.

Responsibilities 

• Participate in the design, implementation, testing & support of the Secure Bootrom and Secure Bootloader solutions.
• Participate in automated testing of the pre-silicon verification (via FPGA emulations), and post-silicon bring up, verification, and debug, focusing on Secure Bootrom and Bootloader.
• Testing of runtime cryptographic operations utilizing supported hardware accelerators.
• Work closely with the SQA and System Test team to help define and implement test cases for security deliverables to ensure complete coverage. 
• Work with other team members to implement the hardware abstraction layer (HAL) and board support package (BSP) of the SDK.

Qualifications 

• BS/MS (EE, CE, or CS) with embedded projects utilizing both bare metal and RTOS systems/real-time environments. 
• 1 year of work experience or internship working with Embedded Security, cryptography, and secure boot concepts.
• Exposure to cryptographic algorithms and protocols, including Public Key Infrastructure, symmetric encryption algorithms, hashing, etc.
• Understanding of security implications for the embedded systems, and familiarity with IoT security concepts  (TrustZone, CryptoCell, and secure boot)
• Classroom or work experience developing embedded C and ARM assembly language in a project setting with a focus on system initialization and low-level code.
• Strong proficiency in Python
• Experience with at least one MCU IDE from ARM, Keil, IAR, Eclipse, or other
• Excellent problem-solving skills dealing with issues related to HW/SW debug
• Hands-on experience with lab equipment such as oscilloscopes, logic analyzers, etc., for debugging issues.
• Understanding of software testing and test automation principles.

 What you need 

We're seeking passionate technologists who thrive on pushing the boundaries, solving complex challenges, and driving transformative solutions. 

At Ambiq, you'll collaborate with a dynamic team that values relentless innovation, customer-centric thinking, and continuous learning. If you're a self-motivated, creative problem-solver eager to push technological limits and make a meaningful impact in energy efficiency, this is your opportunity to grow, excel, and turn groundbreaking ideas into reality. 

Most importantly, the successful candidate will be able to live the Ambiq Shared Values: 

• Innovate: We tenaciously find ways to break down the barriers to possible solutions 
• Collaborate: We proactively communicate and encourage each other to be better. 
• Focus: We keep the voice of the customer at the center of everything we do. 
• Learn: We strive for continuous improvement and are always curious. 
• Achieve: We execute on quality and follow through on our commitments. 

This role will be on-site 5 days a week in NW Austin.

Scope

As a member of the team at Ambiq, an Sr. Staff Embedded Software Engineer (Security),  will provide technical and team leadership in extending and supporting Ambiq’s Secure Bootrom/Bootloader and SDK for the Apollo SoC and emulation platforms.

This role will work within our global MCU software development team, closely with the architecture team and local MCU SoC design teams, focusing on MCU software development and testing.

A successful candidate should be team-oriented, fast-learning, result-driven, and self-motivated with an “always learning” mindset. He/She will have an inquiring spirit and be comfortable in a lab environment, working hands-on with bare metal hardware and debugging tools for embedded systems.

The candidate will be involved in maintaining and extending the Secure Boot ROM, Secure Bootloader, and security aspects of the SDK for Ambiq MCU products from concept through release.

Responsibilities

• Technical Leadership within the MCU Software team. Lead the technical planning, work assignments, and implementation for the new products and new features to be implemented by the MCU software team.
• As the team scales, there's a potential path to managing a small to mid-size team. The candidate is someone who's excited to grow into a player-coach role over time.
• Work with the teams, e.g., Design, Architecture, Verification, and Applications, to define and implement new security features from design to production.
• Participate in testing and verification of pre-silicon (via FPGA emulation), and post-silicon (first Silicon), and debug of issues found, focusing on Secure Bootrom and Bootloader and the hardware features supporting them.
• Integration and Testing of runtime cryptographic operations utilizing the embedded hardware accelerators.
• Work closely with the SQA and System Test team to help define and implement test cases for security deliverables to ensure full coverage.
• Work with other team members to implement the hardware abstraction layer (HAL) and board support package (BSP) of the SDK.

Qualifications

• BS/MS (EE, CE, or CS) with 10+ years of embedded projects utilizing both bare metal and RTOS systems/real-time environments.
• 3+ years of team management experience preferred
• Expert-level proficiency in C, with C++ and object-oriented extensions.
• Embedded Expertise: Strong knowledge of ARM architectures, RTOS, and low-level drivers (I2C, SPI, UART).
• Security Expertise: Experience with Secure Boot, PKI, encryption (AES, RSA, ECC), and embedded security (TrustZone, CryptoCell).
• Experience: Bachelor’s or Master's in CS/EE with 5+ years of relevant embedded security experience.
• Familiarity with debuggers (JTAG, Saleae), Git, and scripting languages (Python, Bash).
• Understanding of security implications for the embedded systems, and familiarity with IoT security concepts (TrustZone, CryptoCell, and secure boot)
• Strong proficiency in Python
• Use of gcc and Arm compilers and MCU IDEs from ARM, Keil, IAR, Eclipse or others
• Excellent problem-solving skills dealing with issues related to HW/SW debug, FPGA/Silicon testing
• Technical Leadership of projects utilizing CI/CD development and automated testing principles.
• Strong documentation skills, mentorship of junior engineers, and ability to work in cross-functional teams. 

**Must be currently authorized to work in the United States for any employer. We do not sponsor or take over sponsorship of employment visas (now or in the future) for this role.

This role will be on-site 5 days a week in NW Austin.  Must have the right to work in the US without visa sponsorship now or in the future. 

Scope

As the Software Architect at Ambiq, you will drive the software architecture and requirements for our latest family of low-power Edge AI MCUs.  As a Software Architect, you will be working closely with our SoC hardware architects, product marketing, and our IP vendors to develop solid functional allocations and requirements for our software development and system test teams.  The role will cover the areas of multi-processor communications, data movement acceleration, virtual memory management, dynamic resource allocation, power optimization, and debug tools.  You will be embedded into Ambiq’s software development teams as the subject matter expert for the duration of the product development.   

The successful candidate will have extensive experience in the early-stage software development process.  The candidate must have strong experience in embedded software programming on ARM Cortex-M processors using RTOS.  They must be familiar with methods for functional allocation, requirements traceability, Software Requirement Specification content, and make vs. buy analysis for commercial and open-source software.  

Responsibilities 

• Requirements analysis based on disparate and preliminary information from SoC hardware architecture team, product marketing, other software architects, and software development teams resulting in contributions to a software requirements specification for the device. This should include any software prototyping required to refine the architectural understanding and requirements. 
• Working closely with our field, product marketing, and system test teams to understand our Alpha customer use cases and their impact on requirements and testability. 
• Engaging during the software implementation and test phases to review designs, test plans, code, and test case results as a SME for certain aspects of the SoC software architecture. 
• Support performance and power optimization of the areas for which you are responsible. 
• Define and enforce architectural standards, guidelines, and best practices. 
• Collaborate with cross-functional teams to align architectural decisions with overall business objectives. 
• Diagnose and resolve complex technical issues and recommend trade-offs between software and hardware implementations. 
• Collaborate effectively with cross-functional teams to achieve project goals. 
• Mentor and guide junior team members. 

 Qualifications 

• A Bachelor's of Science or Master's in Electrical Engineering, Computer Engineering, or Computer Science. 
• 12+ years of experience developing embedded software for real-time environments (bare metal and RTOS). 
• Experienced in code development in C/C++ and assembly language for embedded targets using ARM Cortex-M processors. 
• Experience in writing software requirements specifications with an eye towards customer use cases, derived software requirements, and testability on FPGA-based emulation platforms, as well as full system reference designs. 
• Experience with asymmetric multicore systems and control/data plane interaction, including inter-processor communication via remote processor messaging frameworks (e.g., OpenAMP or RPMsg). 
• Experience with general-purpose data movement engines, memory management units, memory protection, L1/L2 caches, shared memories, and dual-port memories. 
• Experience in power optimization for embedded systems is desirable. Familiarity with voltage and frequency scaling, clock gating, sleep/wake cycles, and low-power modes of processors and peripherals.
• Familiarity with at least one MCU IDE on Windows from ARM/Keil, IAR, Eclipse, or others. 
• Familiarity with Trust Zone for M-Class microcontrollers and/or Trusted Firmware for microcontrollers is preferred. 
• Experience with Graphics, Display and Audio/Video processing in embedded systems preferred. 
• The candidate must be able to independently manage assigned tasks, prioritize workload, and meet deadlines with minimal supervision. Proactive problem-solving skills and the ability to seek clarification when needed are essential. 

Austin, TX – Onsite (5 days/week)
U.S. Work Authorization Required (No Sponsorship Available)

Architect the Software Foundation for Ultra-Low-Power Edge AI Silicon

Ambiq designs and ships ultra-low-power Edge AI MCUs that enable real-time intelligence directly on device.

We are expanding our Austin engineering organization and hiring a Principal Embedded Software Architect to define the software architecture and requirements for our next-generation Edge AI MCU platforms.

This role sits at the hardware/software boundary — partnering directly with SoC architects, product teams, IP vendors, and embedded software leaders to shape how our silicon is exposed, controlled, optimized, and validated.

You won’t just write code.
You will define how the system behaves.

What You’ll Own

As Principal Architect, you will:

• Define the software architecture for next-generation low-power Edge AI MCUs

• Drive early-stage functional allocation between hardware and software

• Develop and refine Software Requirements Specifications (SRS) tied to real customer use cases

• Lead architectural decisions across:

  • Multi-processor communication

  • Control/data plane separation

  • Data movement acceleration

  • Memory management and protection

  • Dynamic resource allocation

  • Power optimization strategies

  • Debug and visibility tooling

• Partner with SoC architects to influence hardware/software trade-offs

• Support software prototyping to validate architectural decisions

• Act as architectural SME through implementation, validation, and bring-up phases

• Review designs, test plans, and implementation details to ensure alignment with architectural intent

• Mentor engineers and define best practices across embedded teams

This is a high-impact architectural role influencing multiple MCU generations.

Technical Environment

You will work deeply across:

• ARM Cortex-M architectures

• Bare metal and RTOS-based systems

• Asymmetric multi-core systems

• Inter-processor communication (OpenAMP, RPMsg, etc.)

• Data movement engines and acceleration blocks

• MMU/MPU, caches, shared memory, dual-port memory

• Power management (DVFS, clock gating, low-power states)

• FPGA-based emulation platforms and full reference systems

You will be embedded within engineering teams while influencing cross-functional decisions across silicon and software domains.

What We’re Looking For

Required Experience

• BS or MS in EE, CE, or CS

• 12+ years developing embedded software for real-time systems

• Deep experience on ARM Cortex-M platforms

• Strong C/C++ (assembly experience preferred)

• Experience defining and writing Software Requirements Specifications (SRS)

• Strong understanding of:

  • Functional allocation

  • Requirements traceability

  • Testability across pre-silicon and post-silicon platforms

• Experience with asymmetric multicore architectures

• Strong knowledge of memory systems, data movement, and processor interaction

• Ability to independently drive architectural decisions

Preferred Experience

• Power optimization strategies in embedded systems

• TrustZone for M-class microcontrollers

• Trusted firmware environments

• Graphics, display, or audio/video processing

• Experience working with IP vendors and external silicon partners

Why This Role Is Different

• Direct architectural influence on Edge AI MCU platforms

• Close collaboration with silicon architects and IP vendors

• Ownership across early-stage definition through validation

• Opportunity to shape hardware/software trade-offs that impact power, performance, and scalability

• Austin-based collaboration culture with tight hardware/software integration

This is a principal-level role for engineers who want to define system behavior — not just implement features.

Location & Work Authorization

Austin, TX – Onsite 5 days per week
Must be authorized to work in the United States. We do not sponsor or transfer visas for this role.

Company Overview:

Allen Control Systems (ACS) is a cutting-edge defense startup founded by two former Navy electrical engineers with a proven track record in robotics and software. We are developing a small, autonomous gun turret that employs advanced computer vision and control systems to precisely target and neutralize small drones and loitering munitions. Our innovative approach requires overcoming significant technical challenges, making this an exciting and dynamic environment for experienced engineers.

 With an engineering-first culture, ACS values technical excellence and innovation. Backed by our founders' successful exits from two previous ventures acquired for a combined $180M in 2022, we are committed to ensuring that the groundbreaking technologies we develop have a real-world impact.

Position Overview:

We are seeking a highly skilled Embedded Linux Software Engineer specializing in Jetson hardware platforms and driver development. The ideal candidate will have hands-on experience configuring embedded Linux PCs such as NVIDIA Jetson, writing Linux drivers, and integrating custom hardware. You will play a critical role in enabling high-performance computer vision and control applications by ensuring reliable low-level software support for our autonomous systems.

What You'll Do:

• Develop and maintain Linux kernel drivers for Jetson-based platforms, supporting Ethernet NICs, USB devices, and MIPI cameras.
• Write and optimize drivers for custom PCIe devices, FPGAs, and other high-performance peripherals.
• Configure, customize, and optimize embedded Linux distributions for NVIDIA Jetson platforms to meet performance and reliability requirements.
• Collaborate with hardware and computer vision teams to ensure seamless integration of sensors, accelerators, and custom hardware with embedded software.
• Debug low-level system issues, analyze performance bottlenecks, and implement fixes for real-time applications.
• Produce thorough documentation of driver implementations, hardware interfaces, and configuration processes.

What You'll Need:

• Experience: 3+ years of experience in embedded Linux software development, including driver programming and low-level system configuration.
• Educational Background: Bachelor’s or Master’s degree in Computer Engineering, Computer Science, Electrical Engineering, or related field.
• Embedded Linux: Strong experience building, configuring, and customizing Linux kernels and drivers for embedded platforms.
• Driver Development: Proven experience writing Linux drivers for Ethernet NICs, USB devices, and MIPI camera interfaces.
• Hardware Interfaces: Familiarity with PCIe and FPGA-based systems.
• Languages: Proficiency in C/C++ for kernel and driver development; Python or Bash for scripting and automation.
• Debugging & Testing: Skilled with low-level debugging tools, oscilloscopes, logic analyzers, and performance profiling techniques.

You'll Stand Out:

• NVIDIA Jetson Experience: Direct experience developing software and drivers on NVIDIA Jetson platforms.
• Robotics & Autonomy: Exposure to robotic or autonomous systems requiring real-time responsiveness.
• High-Performance Systems: Experience optimizing code for low-latency, high-throughput embedded applications.
• Networking & Protocols: Knowledge of networking protocols (TCP/IP, UDP) and peripheral communication standards (I2C, SPI, CAN, UART).
• Open Source Contributions: Demonstrated involvement in kernel or driver-related open-source projects.

What We Offer:

• Competitive salary
• ACS Equity Package
• Health, Dental, Vision Insurance
• Paid Time Off

Allen Control Systems is an Equal Opportunity Employer, providing equal employment opportunities to all employees and applicants for employment. Allen Control Systems prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.

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